Method and apparatus for implementing single/dual packed...

Details Method and apparatus for implementing single/dual packed... Method and apparatus for implementing single/dual packed...

2005-12-13

2005-12-13

Ngo, Chuong Dinh (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S523000

Reexamination Certificate

active

06976049

ABSTRACT:
The present invention relates to a method and system for providing a single accumulatable packed multi-way addition instruction having the functionality of multiple instructions without causing any timing problems in the execute stage. Specifically, the accumulatable packed multi-way combination instruction may be associated with at least one destination and a plurality of operands and set a polarity of each of a plurality of source operands derived from the plurality of operands, if requested by the instruction. The instruction also may add selected pairs of the plurality of source operands in predetermined orders to obtain at least one result and, if requested by the instruction, accumulating the plurality of results to obtain at least one accumulated result; output at least one predetermined pair of the at least one result and the at least one accumulated result; and accumulate condition codes for each of the at least one result and the at least one accumulated result, if requested by the instruction.

REFERENCES:
patent: 4334273 (1982-06-01), Ikeda
patent: 6078941 (2000-06-01), Jiang et al.
patent: 6141673 (2000-10-01), Thayer et al.
patent: 6658578 (2003-12-01), Laurenti et al.
patent: 2002/0143837 (2002-10-01), Duborgel
patent: 2003/0225998 (2003-12-01), Khan et al.

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