Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Phase shift by less than period of input
Reexamination Certificate
2001-09-20
2004-01-13
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Phase shift by less than period of input
C327S238000, C327S248000, C327S255000
Reexamination Certificate
active
06677796
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the implementation of time delays, and more specifically, to a system and a method of implementing high precision time delays that can be utilized in an impulse radio system for significant system improvements.
2. Background of the Invention and Related Art
It is very common for electronic systems to require digitally controlled variable time delays between signals. If the desired delay can be achieved with a smallest step size as big as a clock in a synchronous system, then a counter and a comparator can provide the desired delay. The previous methodologies and structure to accomplish this are illustrated in
FIG. 1
wherein clock
10
and reset
35
are inputs to counter
15
. The output of counter
15
is input to digital compare
25
which has delay count
30
as prior input, thus enabling delay out
25
.
If the desired delay can be achieved with a smallest step size, which can be as big as the propagation time of a logic gate in a digital system, then a tapped delay line with digital selection of the delay tap can provide the desired delay as in
FIG. 2
at
205
. Clock
205
provides tap inputs
215
. Delay count
225
thus allows for a delay out
210
which can correspond to a desired delay by simply choosing the delay tap.
If the desired delay can be achieved with a smallest step size, which must be smaller than the propagation time of a logic gate in a digital system, then a voltage ramp into a variable threshold trigger device is often used where the delay is affected by digitally controlling the trigger voltage (threshold) of the trigger device. This is illustrated in
FIG. 3
wherein clock
305
is input to a voltage ramp device
310
, the output of which is input to an analog compare
315
. A second input to said analog compare
315
is from a delay count
325
passing through a digital to analog converter
330
. Thus, the output of analog compare
315
is a delay out of a smallest step size that can be smaller than the propagation time of a logic gate.
The technique in
FIG. 3
suffers from the requirement that the variable threshold trigger device must be implemented with a great many (for example
256
) perfectly equal step sizes in the trigger voltage, as well as requiring a voltage ramp, which is perfectly linear over the entire range of the steps. To the extent that either the ramp deviates from perfect linearity or the threshold step sizes deviate from perfectly uniform steps, then the resulting time delays will include undesirable non-uniform increments between steps.
A time delay technique which overcomes the aforementioned problems with the voltage ramp in
FIG. 3
has been addressed in a patent application entitled, “Precision Timing Generator System and Method”, Ser. No. 09/146,524, filed Sep. 3, 1998 invented by Preston Jett and with a common assignee of the present invention. Said patent is incorporated herein by reference in its entirety and the techniques for overcoming the aforementioned shortcomings illustrated in
FIG. 3
will be referred to as the “Jett delay technique”. As illustrated in
FIG. 4
, the Jett delay technique uses a quadrature approach wherein sine and cosine values are picked, which result in the most uniform possible amplitude of the resulting delayed sine wave and wherein the input clock signal
405
is a sine wave, which is processed into two intermediate phase shifted signals where one intermediate signal is phase shifted forward 45 degrees
410
and the other intermediate signal is phase shifted backward 45 degrees
415
. These two intermediate signals are then multiplied, at
420
, by digitally specified scaling quantities and summed together, at
425
, to produce an output signal with precisely controlled time delay. The digital specific scaling quantities are provided by inputting a delay count
435
to a lookup table
440
and outputting said result to the respective multipliers after having passed through digital to analog converters
445
and
450
.
The difficulty with the technique shown in
FIG. 4
can be illustrated by considering the specific example of a delay design which is required to produce 256 steps. The look-up tables (e.g.,
440
in
FIG. 4
) containing the scaling factors for the leading and trailing signals are most conveniently implemented in devices fabricated with CMOS, but the actual analog signal processing is most conveniently done with devices fabricated in Gallium Arsinide or Silicon Germanium (SiGe) where faster electronic devices are available. For this example, we assume that the faster devices are fabricated on a SiGe device. For the case of 256 delay steps, the Jett invention requires eight bits of delay specification, which index into a CMOS look-up table, which, in turn, provides eight bits of scaling factor for both the leading and lagging signals. The resulting dilemma is that it is necessary to move 16 bits from the CMOS device to the SiGe device. In the Jett invention, the values in the CMOS lookup table were the values of the sine and cosine functions corresponding to the number of degrees of delay that was desired.
Thus a strong need to overcome the limitations of existing systems and methods of implementing precision time delays exists.
SUMMARY OF THE INVENTION
Briefly stated, the present invention provides a system and method of implementing precision time delays that provides important and novel improvements over prior techniques of implementing time delays by utilizing a new strategy for selecting the values in the sine and cosine lookup tables. Sine and cosine values which result in non-uniform amplitudes enable increased overall accuracy with fewer bits communicated from the look-up tables to the analogue portion of the system. Further, herein is provided the addition of a variable amplitude threshold crossing capability following the combining of the sine and cosine signals. The time delay accuracy of the resulting phase and amplitude hybrid system can be improved either by increasing the number of bits in the sine/cosine phase management section or by increasing the number of bits in the amplitude section. An optimum strategy for choosing the number of bits used in the phase and amplitude sections for the best overall delay accuracy with the fewest overall control bits is also enabled.
Therefore, it is an object of the present invention to provide a system and method of implementing precision time by utilizing a new strategy for selecting the values in the sine and cosine lookup tables.
It is another object of the present invention to provide sine and cosine values which result in non-uniform amplitudes.
It is still another object of the present invention to provide a variable amplitude threshold crossing capability following the combining of the sine and cosine signals.
It is yet another object of the present invention to provide an optimum strategy for choosing the number of bits used in the phase and amplitude sections.
REFERENCES:
patent: 2716236 (1955-08-01), Reinish
patent: 3376504 (1968-04-01), Chick
patent: 3461452 (1969-08-01), Welter
patent: 5644260 (1997-07-01), DaSilva et al.
patent: 5748891 (1998-05-01), Fleming
patent: 5774493 (1998-06-01), Ross
patent: 5928293 (1999-07-01), Jobling et al.
patent: 6002708 (1999-12-01), Fleming et al.
patent: 6137372 (2000-10-01), Welland
patent: 6304623 (2001-10-01), Richards et al.
Brethour Vernon R.
Confer Ryan N.
Pendergrass Marcus H.
Finn James S.
Time Domain Corp.
Wells Kenneth B.
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