Patent
1996-12-11
1998-06-09
Treat, William M.
39580023, G06F 946
Patent
active
057649715
ABSTRACT:
An apparatus for producing in a superscalar pipelined system out-of-order execution and in-order completion of a set of macroinstructions, wherein the set of macroinstructions are translated into a set of microinstructions and the microinstructions are executed by the pipelined system and wherein at least some of said macroinstructions translate into more than one microinstruction, the apparatus including a result completion register having a plurality of entry fields each of which is used to indicate a completion state of a different corresponding microinstruction among the set of microinstructions; an interrupt condition register having a plurality of entry fields each of which is used to specify an occurrence of an interrupt condition during fetching, decoding, and executing a corresponding microinstruction among the set of microinstructions; an instruction size register having a plurality of entry fields which are used to identify locations of boundaries between macroinstructions among the set of microinstructions; a priority encoder which receives input from the result completion register and the instruction size register and which during operation generates an output indicating when all of the microinstructions of a next-in-line macroinstruction have been executed; and a retirement controller which receives the output from the priority encoder and which during operation in response to the output of the priority encoder retires the next-in-line macroinstruction when said output indicates that all of the microinstructions of the next-in-line macroinstruction have been executed.
REFERENCES:
patent: 4438489 (1984-03-01), Heinrich et al.
patent: 5075844 (1991-12-01), Jardine et al.
patent: 5109381 (1992-04-01), Duxbury et al.
patent: 5193158 (1993-03-01), Kinney et al.
patent: 5283891 (1994-02-01), Suzuki et al.
patent: 5307504 (1994-04-01), Robinson et al.
patent: 5325536 (1994-06-01), Chang et al.
patent: 5448705 (1995-09-01), Nguyen et al.
patent: 5542058 (1996-07-01), Brown, III et al.
patent: 5659721 (1997-08-01), Shen et al.
patent: 5687338 (1997-11-01), Boggs et al.
patent: 5692170 (1997-11-01), Isaman
Walker, et al., "Interrupt Processing in Concurrent Processors," IEEE, 36-46 (Jun. 1995).
Smith, et al., "Implementing Precise Interrupts in Pipeland Processors," IEEE, 37:562-573 (May 1988).
Chang Ching-Tang
Huang Bing-Huang
Lin Shih-Yin
Shang Shi-Sheng
Industrial Technology Research Institute
Treat William M.
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