Method and apparatus for implementing power of two floating...

Details Method and apparatus for implementing power of two floating... Method and apparatus for implementing power of two floating...

2006-11-28

2006-11-28

Ngo, Chuong D. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

07143126

ABSTRACT:
A method and apparatus are provided for implementing a power of two estimation function in a general purpose floating-point processor. A floating point number is stored within a memory. The floating point number includes a sign bit, a plurality of exponent bits, and a mantissa having an implied bit and a plurality of fraction bits. In response to a floating-point instruction, the mantissa is partitioned into an integer part and a fraction part, based on the exponent bits. A floating-point result is provided by assigning the integer part of the floating point number as an unbiased exponent of the floating-point result, and by utilizing combinational logic hardware for converting the fraction part of the floating point number to a fraction part of the floating point result.

REFERENCES:
patent: 4078250 (1978-03-01), Windsor et al.
patent: 4583180 (1986-04-01), Kmetz
patent: 5365465 (1994-11-01), Larson
patent: 6178435 (2001-01-01), Schmookler
patent: 6289367 (2001-09-01), Allred

Affiliated with

Also associated with

Rating

Method and apparatus for implementing power of two floating... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for implementing power of two floating..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for implementing power of two floating... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3653980