Method and apparatus for implementing inter-processor interrupts

Details Method and apparatus for implementing inter-processor interrupts Method and apparatus for implementing inter-processor interrupts

1989-12-04

1992-08-04

Chan, Eddie P.

Boots, shoes, and leggings

364DIG1, 3642281, 3642302, 36424291, G06F 1300, G06F 1516

Patent

active

051367149

ABSTRACT:
An inter-processor interrupt mechanism is implemented in a shared-memory multi-processor system. A dedicated halfword for each processor in said multi-processor system is provided in the shared memory restricted in use to the generation and control of inter-processor interrupts. No data in any dedicated shared-memory location can be altered by any processor unless it has "captured" the location by executing a test and set halfword instruction and a captured shared-memory location being released only by executing a store halfword instruction. An address comparator and a zero detector are added as adjunct operations to read-modify-write logic of each processor's memory interface. When any instruction is executed and its operand address agrees with that contained in the address comparator, an inter-processor interrupt request is generated if zero is not detected on all predefined data bits being written to memory. If a zero is detected on all predefined data bits being written to memory, the inter-processor interrupt request is removed.

REFERENCES:
patent: 4128881 (1978-12-01), Yamamoto et al.
patent: 4561051 (1985-12-01), Rodman et al.
patent: 4941083 (1990-07-01), Gillett, Jr. et al.
patent: 4949239 (1990-08-01), Gillett, Jr. et al.

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