Method and apparatus for implementing frame header...

Details Method and apparatus for implementing frame header... Method and apparatus for implementing frame header...

2007-05-29

2007-05-29

Nguyen, Hanh (Department: 2616)

Multiplex communications

Communication techniques for information carried in plural...

Adaptive

C370S389000, C370S412000, C370S503000

Reexamination Certificate

active

10185556

ABSTRACT:
A method and apparatus are provided for implementing frame header alterations using byte-wise arithmetic logic units (ALUs). First and second stage alteration engines include a plurality of first stage byte-wise arithmetic logic units (ALUs). Each ALU includes inputs for receiving frame data, command data, register data, and commands, and register data and data outputs. The first and second stage byte-wise ALUs respectively perform the received first and second stage commands and the second stage ALUs provide altered frame data output. The commands enable operations such as load, add, and, or, move, and the like used by the two-stages of byte-wise ALUs forming the alteration engines to perform the alterations or combine new header data into a stream of frame data.

REFERENCES:
patent: 5669010 (1997-09-01), Duluk, Jr.
patent: 5859992 (1999-01-01), Tran et al.
patent: 6085311 (2000-07-01), Narayan et al.
patent: 6731652 (2004-05-01), Ramfelt et al.
U.S. Appl. No. 185,552, filed Jun. 27, 2002, entitled “Method and Apparatus for Implementing Frame Header Alterations”.
U.S. Appl. No. 180,993, filed Jun. 27, 2002, entitled “Method and Apparatus for Implementing Alterations on Multiple Concurrent Frames”.

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