Coded data generation or conversion – Digital code to digital code converters
Reexamination Certificate
2000-12-29
2004-02-24
Young, Brian (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
Reexamination Certificate
active
06696988
ABSTRACT:
FIELD
The present invention is related to priority encoders. More particularly, the present invention is related to the use of circular priority encoders.
BACKGROUND
Priority encoders are circuits that serve to acknowledge a request having a highest priority (or rank) from among a plurality of requests arriving as active signals to the priority encoder. A request acknowledgment may include enabling a circuit (such as a microprocessor) so that the circuit may execute the task corresponding to the request.
A priority encoder may receive one or a plurality of simultaneous requests on respective request lines (i.e., input lines) assigned with respective ranks, for example from
1
to n. The priority encoder may acknowledge one request at a time through acknowledgment lines. In some encoders, the acknowledgment lines directly correspond to request lines, and the encoder transmits the acknowledged request only on the acknowledgment lines. In some priority encoders, the acknowledgment lines may provide a binary rank of the acknowledged request.
In linear priority encoders, the priorities (or ranks) assigned to the request lines may be distinct. That is, the priorities may be assigned by decreasing order to the ranks of the request lines by starting with a highest rank. Linear encoders may acknowledge the request of the highest rank.
Linear encoders may be implemented as a non-sequential logic circuit, of a carry propagation type, that acknowledges the request of the highest rank after any change in the states of the request lines. The actual delay may depend on the carry propagation time of the circuitry.
REFERENCES:
patent: 5160923 (1992-11-01), Sugawara
patent: 5568485 (1996-10-01), Chaisemartin
patent: 6385631 (2002-05-01), Chen et al.
Jinn-Shyan Wang et al., “High-speed and Low-Power CMOS Priority Encoders”,IEEE Journal of Solid-State Circuits, vol. 35, No. 10, Oct. 2000, pp. 1511-1514.
Jinn-Shyan Wang et al., “A High-Speed Single-Phase-Clocked CMOS Priority Encoder”,ISCAS 2000, IEEE International Symposium on Circuits and Systems, May 28-31, 2000, Geneva Switzerland, pp. V-537-540.
Rozo Hashemian, “A High Speed Compact Priority Encoder”, pp. 197-200, no date.
Masato Yoneda et al., “A 1 Mbit NAND-Type Content Addressable ROM with a Variable Length Match Function”,1992 Symposium on VLSI Circuits Digest of Technical Papers, pp. 86-87.
Intel Corporation
LeMoine Patent Services, PLLC
Young Brian
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