Method and apparatus for implementing an algorithm associated wi

Details Method and apparatus for implementing an algorithm associated wi Method and apparatus for implementing an algorithm associated wi

1983-05-13

1986-08-19

Eng, David Y.

Boots, shoes, and leggings

G06F 1202, G06F 1208, G06F 1212

Patent

active

046073310

ABSTRACT:
A circuit and method for implementing a predetermined data replacement algorithm associated with a fast, low capacity cache, such as least recently used (LRU), which is fast and which minimizes circuitry is provided. A latch stores the present status of the replacement algorithm, and an address control signal indicates which one of n sets of stored information in the cache has been most recently accessed, where n is an integer. The predetermined algorithm is implemented by a predetermined permutation table stored in a translator which provides an output signal in response to both the present status of the replacement algorithm and the address control signal. The output signal indicates which one of the n sets of stored information in the cache may be replaced with new information.

REFERENCES:
patent: 3958228 (1976-05-01), Coombes et al.
patent: 3967247 (1976-06-01), Andersen
patent: 4332010 (1982-05-01), Messina et al.
patent: 4400770 (1983-08-01), Chan et al.
patent: 4403288 (1983-09-01), Christian et al.

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