Method and apparatus for implementing alterations on...

Multiplex communications – Pathfinding or routing – Switching a message which includes an address header

Reexamination Certificate

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Details

C370S470000, C712S028000, C712S032000, C710S005000, C710S007000

Reexamination Certificate

active

10180993

ABSTRACT:
A method and apparatus are provided for implementing frame header alterations on multiple concurrent frames. Each of a plurality of frame data alteration engines includes a pair of a command decoder and an associated data aligner. A command buffer arbiter sequentially receives frame alteration commands and sequentially selects one of the frame data alteration engines for the sequentially received frame alteration commands. Each command decoder receives and decodes frame alteration commands and provides frame alignment commands and alteration instructions and each associated data aligner receives frame data and selectively latches data bytes of the received frame data responsive to the frame alignment commands and sequentially provides an aligned frame data output of a predefined number of bytes. An alteration engine receives sequentially provided aligned frame data output and alteration instructions from a selected one the plurality of frame data alteration engines and provides sequential altered frame data responsive to the received alteration instructions.

REFERENCES:
patent: 6259699 (2001-07-01), Opalka et al.
patent: 6694380 (2004-02-01), Wolrich et al.
“DSP MircoComputers ADSP-2181/ADSP-2183” by Analog Device , 1996 month not available.
“Intel IXP1200 Network Processor Family Hardware Reference manual” by Intel Dec. 2001.
“Distributed Computing Applied to a VLSI Chip” by Maha M. Zaghloul published in IEEE 1990 month not available.
“Intel IXP1200 Network Processor Family Microcode Programmer's Reference manual” by Intel Mar. 2002(Only provided Cover and Content pages).

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