Method and apparatus for implementing a in-order termination bus

Details Method and apparatus for implementing a in-order termination bus Method and apparatus for implementing a in-order termination bus

1994-12-22

1997-12-16

Geckil, Mehmet B.

395287, 395290, G06F 1336

Patent

active

056995164

ABSTRACT:
A bus protocol is provided for pipelined and/or split transaction buses (18,48) which have in-order data bus termination and which do not require data bus arbitration. The present invention solves the problem of matching the initial address request by a bus master (12, 13, 42) to the corresponding data response from a bus slave (14, 15, 44) when the bus (18, 48) used for master-slave communication is a split-transaction bus and/or a pipelined bus. Each bus master (12, 13, 42) and each bus slave (14, 15, 44) has a counter (30-33, 75-76) which is used to store a current pipe depth value (21, 51) from a central pipe counter (16, 72). A transaction start signal (20, 50) and a transaction end signal (22, 52) are used to selectively increment and decrement the counters (30-33, 75-76).

REFERENCES:
patent: 5050066 (1991-09-01), Myers et al.
patent: 5191649 (1993-03-01), Cadambi et al.
patent: 5255373 (1993-10-01), Brockmann et al.
patent: 5345562 (1994-09-01), Chen
patent: 5345578 (1994-09-01), Manasse
patent: 5513327 (1996-04-01), Farmwald
patent: 5546546 (1996-08-01), Bell et al.
patent: 5588125 (1996-12-01), Bennett

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