Method and apparatus for implementing a fully-associative transl

Details Method and apparatus for implementing a fully-associative transl Method and apparatus for implementing a fully-associative transl

1996-09-16

1999-07-27

Maung, Zarni

Electrical computers and digital processing systems: processing

Architecture based instruction processing

711200, 711202, 711203, 711206, 711207, G06F 1210, G06F 1212

Patent

active

059283521

ABSTRACT:
Some virtual memory systems allow more that one memory page size. To quickly translate virtual page addresses into physical page addresses, a multi-page size translation look-aside buffer is needed. The multi-page size translation look-aside buffer has a virtual address array and a physical address array. The virtual address array has a set of virtual address entries that are compared to a received virtual address. The virtual address array entries have virtual address tag field, a valid bit, and a page size bit. The page size bit defines the size of the memory page and thus defines the number of bits in the virtual address that must be matched with virtual address tag bits in the virtual address array. The valid bit indicates if the entry is valid or not. When a hit is detected in the virtual address array, a corresponding entry in the physical address array is activated. The physical address array comprises a physical page address and a set of page attributes. The physical address array also has a locked bit and an access bit that are used to implement a translation look-aside buffer replacement scheme.

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