Method and apparatus for implementing a DMA timeout counter feat

Details Method and apparatus for implementing a DMA timeout counter feat Method and apparatus for implementing a DMA timeout counter feat

1994-10-25

1998-10-20

Shin, Christopher S.

395840, 395882, 395868, 395309, 395500, G06F 300

Patent

active

058261079

ABSTRACT:
A high performance Local Bus Peripheral Interface (LBPI) for a computer local bus and high performance peripheral interface(s) uses a pipelined architecture to increase use of available data transfer bandwidth. The LBPI coupled between the computer local bus and peripheral interface(s) is provided a pipelined architecture including a Read Ahead Buffer, a Read Ahead Counter, a Data Out Latch, and a controlling State Machine with a Configuration Register. The LBPI supports DMA and PIO data transfers on the peripheral side. In another embodiment, the LBPI translates memory data transfers into IO data transfers to improve efficiency of IO data transfers. A DMA Timeout Counter is used during DMA mode data transfer operations to prevent the system from indefinitely waiting for an appropriate DMA Request Signal from a selected peripheral. During a DMA mode data transfer operation, forced interrupts may be generated and transmitted to the host in order to emulate a PIO mode data transfer operation. During a DMA mode data transfer operation, an imposed status or "Fake 3F6" register is utilized to transmit status information to the host system.

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