Electrical computers and digital processing systems: processing – Processing architecture – Long instruction word
Reexamination Certificate
2000-03-30
2003-12-02
Donaghue, Larry D. (Department: 2154)
Electrical computers and digital processing systems: processing
Processing architecture
Long instruction word
C712S215000, C717S161000
Reexamination Certificate
active
06658551
ABSTRACT:
FILED OF THE INVENTION
The present invention relates generally to multithreaded processors, and, more particularly, to a method and apparatus for splitting packets in such multithreaded processors.
BACKGROUND OF THE INVENTION
Computer architecture designs attempt to complete workloads more quickly. A number of architecture designs have been proposed or suggested for exploiting program parallelism. Generally, an architecture that can issue more than one operation at a time is capable of executing a program faster than an architecture that can only issue one operation at a time. Most recent advances in computer architecture have been directed towards methods of issuing more than one operation at a time and thereby speed up the operation of programs.
FIG. 1
illustrates a conventional microprocessor architecture
100
. Specifically, the microprocessor
100
includes a program counter (PC)
110
, a register set
120
and a number of functional units (FUs)
130
-N. The redundant functional units (FUs)
130
-
1
through
130
-N provide the illustrative microprocessor architecture
100
with sufficient hardware resources to perform a corresponding number of operations in parallel.
An architecture that exploits parallelism in a program issues operands to more than one functional unit at a time to speed up the program execution. A number of architectures have been proposed or suggested with a parallel architecture, including superscalar processors, very long instruction word (VLIW) processors and multithreaded processors, each discussed below in conjunction with
FIGS. 2
,
4
and
5
, respectively. Generally, a superscalar processor utilizes hardware at run-time to dynamically determine if a number of operations from a single instruction stream are independent, and if so, the processor executes the instructions using parallel arithmetic and logic units (ALUs). Two instructions are said to be independent if none of the source operands are dependent on the destination operands of any instruction that precedes them. A very long instruction word (VLIW) processor evaluates the instructions during compilation and groups the operations appropriately, for parallel execution, based on dependency information. A multithreaded processor, on the other hand, executes more than one instruction stream in parallel, rather than attempting to exploit parallelism within a single instruction stream.
A superscalar processor architecture
200
, shown in
FIG. 2
, has a number of functional units that operate independently, in the event each is provided with valid data. For example, as shown in
FIG. 2
, the superscalar processor
200
has three functional units embodied as arithmetic and logic units (ALUs)
230
-N, each of which can compute a result at the same time. The superscalar processor
200
includes a front-end section
208
having an instruction fetch block
210
, an instruction decode block
215
, and an instruction sequencing unit
220
(issue block). The instruction fetch block
210
obtains instructions from an input queue
205
of a single threaded instruction stream. The instruction sequencing unit
220
identifies independent instructions that can be executed simultaneously in the available arithmetic and logic units (ALUs)
230
-N, in a known manner. The refine block
250
allows the instructions to complete, and also provides buffering and reordering for writing results back to the register set
240
.
In the program fragment
310
shown in
FIG. 3
, instructions in locations L
1
, L
2
and L
3
are independent, in that none of the source operands in instructions L
2
and L
3
are dependent on the destination operands of any instruction that precedes them. When the program counter (PC) is set to location L
1
, the instruction sequencing unit
220
will look ahead in the instruction stream and detect that the instructions at L
2
and L
3
are independent, and thus all three can be issued simultaneously to the three available functional units
230
-N. For a more detailed discussion of superscalar processors, see, for example, James. E. Smith and Gurindar. S. Sohi, “The Microarchitecture of Superscalar Processors,” Proc. of the IEEE (December 1995), incorporated by reference herein.
As previously indicated, a very long instruction word (VLIW) processor
400
, shown in
FIG.4
, relies on software to detect data parallelism at compile time from a single instruction stream, rather than using hardware to dynamically detect parallelism at run time. A VLIW compiler, when presented with the source code that was used to generate the code fragment
310
in
FIG. 3
, would detect the instruction independence and construct a single, very long instruction comprised of all three operations. At run time, the issue logic of the processor
400
would issue this wide instruction in one cycle, directing data to all available functional units
430
-N. As shown in
FIG. 4
, the very long instruction word (VLIW) processor
400
includes an integrated fetch/decode block
420
that obtains the previously grouped instructions
410
from memory. For a more detailed discussion of very long instruction word (VLIW) processors, see, for example, Burton J. Smith, “Architecture and Applications of the HEP Multiprocessor Computer System,” SPIE Real Time Signal Procesing IV, 241-248 (1981), incorporated by reference herein.
One variety of VLIW processors, for example, represented by the Multiflow architecture, discussed in Robert P. Colwell et al., “A VLIW Architecture for a Trace Scheduling Compiler,” IEEE Transactions on Computers (August 1988), uses a fixed-width instruction, in which predefined fields direct data to all functional units
430
-N at once. When all operations specified in the wide instruction are completed, the processor issues a new, multi-operation instruction. Some more recent VLIW processors, such as the C6x processor commercially available from Texas Instruments, of Dallas, Tex. and the EPIC IA-64 processor commercially available from Intel Corp, of Santa Clara, Calif. instead use a variable-length instruction packet, which contains one or more operations bundled together.
A multithreaded processor
500
, shown in
FIG. 5
, gains performance improvements by executing more than one instruction stream in parallel, rather than attempting to exploit parallelism within a single instruction stream. The multithreaded processor
500
shown in
FIG. 5
includes a program counter
510
-N, a register set
520
-N and a functional unit
530
-N, each dedicated to a corresponding instruction stream N. Alternate implementations of the multithreaded processor
500
have utilized a single functional unit
530
, with several register sets
520
-N and program counters
510
-N. Such alternate multithreaded-processors
500
are designed in such a way that the processor.
500
can switch instruction issue from one program counter/register set
510
-N/
520
-N to another program counter/register set
510
-N/
520
-N in one or two cycles. A long latency instruction, such as a LOAD instruction, can thus be overlapped with shorter operations from other instruction streams. The TERA MTA architecture, commercially available from Tera Computer Company, of Seattle, Wash. is an example of this type.
An extension of the multithreaded architecture
500
, referred to as Simultaneous Multithreading, combines the superscalar architecture, discussed above in conjunction with
FIG. 2
, with the multithreaded designs, discussed above in conjunction with FIG.
5
. For a detailed discussion of Simultaneous Multithreading techniques, see, for example, Dean Tullsen et al., “Simultaneous Multithreading: Maximizing On-Chip Parallelism,” Proc. of the 22nd Annual Int'l Symposium on Computer Architecture, 392-403 (Santa Margherita Ligure, Italy, June 1995), incorporated by reference herein. Generally, in a Simultaneous Multithreading architecture, there is a pool of functional units, any number of which may be dynamically assigned to an instruction which can issue from any one of a number of program counter/register set structures. By sharing the
Berenbaum Alan David
Heintze Nevin
Jeremiassen Tor E.
Kaxiras Stefanos
Agere Systems Inc.
Donaghue Larry D.
Ryan & Mason & Lewis, LLP
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