Method and apparatus for identifying faults within a system

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371 28, 371 671, G06F 1122

Patent

active

055703763

ABSTRACT:
Lists of candidate faults within an integrated circuit are generated, for the purpose of fault diagnosis, by performing a partial intersection of fault lists output from a full-scan test such as a JTAG test. The fault lists represent all candidate faults which may be responsible for producing a mismatched bit between an output test vector and an expected test vector provided by the full-scan test. The partial intersection is performed by first determining the number of occurrences of each candidate fault within all lists associated with each mismatched bit. Then, only faults which occur at least a pre-selected number of times are selected. In this manner, lists of candidate faulty gates are generated based on the relative degree of intersection between fault sets. The lists of candidate faulty gates are input to an X-Y location tool which determines the physical location on the integrated circuit of each of the candidate faulty gates to facilitate the efficient examination of each of the candidate faulty gates by test personnel.

REFERENCES:
patent: 4228537 (1980-10-01), Henckels et al.
patent: 5293323 (1994-03-01), Doskocil et al.
patent: 5325309 (1994-06-01), Halaviati et al.
patent: 5377197 (1994-12-01), Patel et al.
patent: 5418792 (1995-05-01), Maamari
Test Generation By Fault Sampling; Agrawal et al; 1988 IEEE.

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