Multiplex communications – Communication techniques for information carried in plural... – Combining or distributing information via time channels
Reexamination Certificate
1999-11-03
2004-11-23
Nguyen, Steven (Department: 2665)
Multiplex communications
Communication techniques for information carried in plural...
Combining or distributing information via time channels
C326S038000, C327S407000
Reexamination Certificate
active
06822976
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally related to the field of electronic circuits and more specifically related to the field of multiplexing circuitry and data processing circuitry.
2. Description of the Related Art
Cascading of multiplexing circuits is well known as a method of creating multiplexing circuits with larger numbers of inputs. A conventional schematic for cascading three multiplexing circuits (MUXes) is illustrated in FIG.
1
B. MUX C is controlled by select signal S
0
, receives as its inputs the outputs of MUX A (G) and MUX B (H), and the output of MUX C (F) is routed to a flip-flop F
4
. Select signal S
0
determines whether the output of MUX A or the output of MUX B is routed through MUX C. Likewise, MUX A receives signals D
0
and D
1
as its inputs, and whether D
0
or D
1
is routed through MUX A to become output G is determined by signal S
1
. MUX B receives signals D
2
and D
3
as its inputs, and signal S
1
likewise controls whether D
2
or D
3
is routed through MUX B to become output H. The following truth table further explains the behavior of the circuit of FIG.
1
B.
D0
D1
D2
D3
S0
S1
G
H
F
d0
d1
d2
d3
0
0
d0
d2
d0
d0
d1
d2
d3
0
1
d1
d2
d1
d0
d1
d2
d3
1
0
d0
d3
d2
d0
d1
d2
d3
1
1
d1
d3
d3
Such a circuit has a delay time
t
d
=MAX(T
delay
MUX
A,T
delay
MUX
B
)+
T
delay
MUX
C
Since the operating frequency of the circuit corresponds to the delay, the operating frequency of the multiplexing circuit is limited by the speed of signals through two stages of the MUX stage for 4:1 selection.
Prior art systems which incorporate multiplexing circuitry often use a configuration of components as illustrated in FIG.
1
A. CPU
101
(a Central Processor or Processor) is coupled to a component referred to as a Host Bridge
105
, and thereby coupled to the rest of the system. Host Bridge
105
is coupled to Memory
103
, the main memory of the system, and Host Bridge
105
is also coupled to I/O Bridge
107
(Input/Output Bridge). I/O Bridge
107
couples to Keyboard
109
, Mouse
111
, and Disk Drive
110
, and may couple to other components in a bus or point-to-point fashion. Through these couplings, CPU
101
is coupled to each component in the system, and may read or write information to each of the devices (within the capabilities of those devices).
Further extending the complexity of the system, PCI Bus
125
(Peripheral Component Interconnect Bus based on the Peripheral Component Interconnect Bus Specification Revision 2.1 or 2.2 from the Portland PCI Working Group as published by Intel Corporation) may be involved in the coupling of Host Bridge
105
to I/O Bridge
107
, and may thereby couple to PCI Agents
120
. Thus, through Host Bridge
105
, CPU
101
may communicate with PCI Agents
120
. While it is advantageous to make PCI Agents
120
available to the system, incorporating the PCI Bus
125
into a coupling or connection between the Host Bridge
105
and the I/O Bridge
107
further complicates the physical devices and layout, and the protocols for communication over that coupling.
SUMMARY OF THE INVENTION
A method and apparatus for high throughput multiplexing of data is described. It includes a circuit including: A first multiplexer having an output, a first input, a second input, and a selector. A second multiplexer having an output, a first input, a second input, and a selector, the output of the second multiplexer coupled to the first input of the first multiplexer. A third multiplexer having an output, a first input, a second input, and a selector, the output of the third multiplexer coupled to the second input of the first multiplexer; and the selector of the first multiplexer to select an input with a stable signal.
REFERENCES:
patent: 4825105 (1989-04-01), Holxle
patent: 5198705 (1993-03-01), Galbraith et al.
patent: 5491431 (1996-02-01), Nasserbakht
patent: 5510742 (1996-04-01), Lemaire
patent: 5815023 (1998-09-01), Webber et al.
patent: 6104731 (2000-08-01), Chow
Lin Hou-Sheng
Riesenman Robert
Blakely , Sokoloff, Taylor & Zafman LLP
Nguyen Steven
Stevens Roberta
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