Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1999-03-11
2001-10-09
Mai, Tan V. (Department: 2121)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S505000, C708S495000
Reexamination Certificate
active
06301594
ABSTRACT:
BRIEF DESCRIPTION IF THE INVENTION
The present invention relates generally to floating-point number operations. More particularly, the present invention relates to exponent adjustment and exception generation for the normalization of floating-point numbers.
BACKGROUND OF THE INVENTION
In most operations on floating-point numbers, such as floating-point addition, the result of the operation is normalized. Normalizing a floating-point number involves shifting the mantissa until the most significant bit of the mantissa is nonzero. The exponent of the number is then adjusted accordingly by increasing or decreasing its value to compensate for the shifting of the mantissa. If the exponent adjustment causes an underflow or some other exceptional condition, an arithmetic exception is generated.
In a floating-point arithmetic circuit, such as a floating-point adder, the circuitry for normalizing the floating-point result (and associated arithmetic exception generation circuitry) typically contains a critical path that limits the speed of the arithmetic circuit. The critical path in the normalization circuitry usually includes a shift count detect circuit that generates a shift count (also called “norm count ” indicating the number of bit positions that the mantissa of the floating-point result is to be shifted for normalization and an exponent adjustment circuit that adjusts the value of the exponent of the result based on the shift count. Because of its impact on the speed of a floating-point adder, it is important to minimize the delay of this critical path.
Various techniques have been used in the prior art to reduce the delay in generating the shift count, including the lead-zero-detection (LOD) and lead-zero-prediction (LOP) schemes. A detailed description of these techniques may be found in a number of references, including the background section of co-pending U.S. patent application Ser. No. 08/883,129, entitled “Norm-Count Detection Method of Floating Point Adder”, which is incorporated herein by reference. The LOD and LOP schemes generate shift counts with a relatively small delay. However, since the shift count produced by these schemes is not exact, the exponent adjustment is only approximate. A second, final exponent adjustment is necessary to produce the exponent of the normalized number, thereby making the exponent adjustment circuit more complex and increasing the time required to generate the exponent of the normalized number.
In view of the shortcomings of these prior art normalization methods, it is an object of the present invention to minimize the delay incurred by exponent adjustment and exception generation for the normalization of floating-point numbers.
SUMMARY OF THE INVENTION
The present invention is a method and circuit for adjusting an exponent of an unnormalized floating-point number to generate an exponent of a normalized floating-point number. The method includes the steps of: (1) generating a shift count indicating the number of bit positions, if any, a mantissa of an unnormalized floating-point number is to be left shifted to normalize the unnormalized floating-point number, (2) generating a right shift indicator indicating the number of bit positions, if any, the mantissa is to be right shifted to normalize the unnormalized floating-point number, (3) incrementing the value of an exponent of the unnormalized floating-point number, (4) concurrently with the incrementing step, complementing a plurality of bits of the shift count and (5) adding the exponent, the shift count and the right shift indicator to generate an exponent of a normalized floating-point number.
The circuit of the present invention includes: (1) a shift count detector circuit to generate a shift count signal indicating the number of bit positions, if any, a mantissa of an unnormalized floating-point number is to be left shifted to normalize the unnormalized floating-point number, (2) a right shift detector circuit to generate a right shift signal indicating the number of bit positions, if any, the mantissa is to be right shifted to normalize the unnormalized floating-point number, (3) an incrementer circuit to increment the value of an exponent of the unnormalized floating-point number, (4) an inverting circuit coupled to the shift count detector circuit to complement a plurality of bits of the shift count signal and (5) an adder circuit coupled to the incrementer circuit, the inverting circuit and the right shift detector circuit to add the exponent, the shift count signal and the right shift signal to generate an exponent of a normalized floating-point number.
In a preferred embodiment of the present invention, the shift count/shift count signal is generated by performing an adding step and a rounding step concurrently. The shift count/shift count signal generated in this manner is produced relatively quickly and is thus called an “early” shift count/shift count signal.
The method and circuit of the present invention may be implemented in a floating-point adder. In these embodiments, the unnormalized floating-point number is the unnormalized result of either a floating-point addition operation or an integer-to-floating-point format conversion operation performed by the floating-point adder.
The method and circuit of the present invention reduces the time required to perform the exponent adjustment by minimizing the number of serially executed steps or critical path gate delays, respectively, used in the exponent adjustment process. The minimization of steps and gate delays in the exponent adjustment process is facilitated by the use of the early shift count/shift count signal.
REFERENCES:
patent: 4779220 (1988-10-01), Nukiyama
patent: 4994996 (1991-02-01), Fossum et al.
patent: 5111421 (1992-05-01), Molnar et al.
patent: 5197023 (1993-03-01), Nakayama
patent: 5471410 (1995-11-01), Bailey et al.
patent: 5757682 (1998-05-01), Schwarz et al.
patent: 5923574 (1999-07-01), Bechade
patent: 6154760 (2000-11-01), Sharangpani
Mai Tan V.
Pennie & Edmonds LLP
Sun Microsystems Inc.
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