Method and apparatus for high-speed block transfer of compressed

Computer graphics processing and selective visual display system – Computer graphic processing system – Plural graphics processors

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345511, 345202, G09G 536

Patent

active

060846003

ABSTRACT:
Graphics display performance is significantly improved by compressing pixel information, by aligning the 8, 16 or 32 bit pixels transferred over a 32-bit Peripheral Component Interface (PCI) bus with the pixels in the display memory, and by avoiding moves of pixel data within display memory. Compression is achieved by not transferring data for pixels that are not modified by the transfer. Rather, a count of unmodified pixel bytes to skip precedes each set of pixel data for contiguous pixels that are modified. Alignment is achieved by ensuring that the boundaries between words within the pixel set transferred matches those within the corresponding target pixels in the display memory. This alignment significantly speeds up modifying pixel data within the display memory. The burden of ensuring this alignment is placed on the applications software that initiates the transfer. For a static image, such as a cockpit, this alignment can be achieved at the time that the image information used by the software is compiled into a bitmap. For a dynamic image, such as a sprite, this alignment can be achieved by compiling all possible word alignments of the sprite's pixel data into different bitmap versions. At run time, the applications software uses the sprite's current location to dynamically select which bitmap version to transfer. In one embodiment, a graphics accelerator interprets the bitmap transferred and updates display memory accordingly. In another embodiment, software executing on the host CPU directly writes pre-aligned pixel data into the display memory.

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