Method and apparatus for high-rate n/n+1 low-complexity modulati

Details Method and apparatus for high-rate n/n+1 low-complexity modulati Method and apparatus for high-rate n/n+1 low-complexity modulati

1998-03-23

2000-01-25

Tokar, Michael

Coded data generation or conversion

Digital code to digital code converters

To or from minimum d.c. level codes

714811, 341 59, H03M 500

Patent

active

060183047

ABSTRACT:
Highly efficient, enhanced RLL and MTR constrained or modulation codes and a unified methodology for generating the same. The new codes also include partial error detection (PED) capability. RLL/PED code rates of 8/9, 16/17, 24/25 and 32/33 or higher are disclosed. The new generalized RLL/PED block coding schemes are derived with fixed length n: n/(n+1)(d=0, k=n-1/l=n), n
+1(0,[n/2]/l=n+4) and m/(n+1)(d=0, k=[n/2]/l=n) for n.gtoreq.5 (where [ ]denotes the enteger part of the argument). The codes n/(n+1)(0,[n/2]/l=n+4) are also shown in a concatenated ECC/modulation architecture, where the modulation decoder, capable of detecting bits in error, generates symbol byte erasures to boost the performance of the outer ECC decoder.

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