Electrical computers and digital processing systems: multicomput – Computer-to-computer protocol implementing
Reexamination Certificate
2005-11-08
2005-11-08
Dharia, Rupal (Department: 2141)
Electrical computers and digital processing systems: multicomput
Computer-to-computer protocol implementing
C709S231000, C709S232000, C709S233000, C370S229000, C370S230000
Reexamination Certificate
active
06963921
ABSTRACT:
A hardware packet accelerator parses incoming packets to retrieve header data for building a frame status and for verifying the incoming packets are part of an established connection with a host. The accelerator includes a connection database that allows retrieval of connection information based on an index constructed from a hashed TCP connection address. The frame status comprises information needed to perform packet re-assembly and is stored in a memory that is local (directly accessible) by a processing device that performs the packet re-assembly. Among other advantages, the processing device does not need to read packet header data from a packet buffer, saving large amounts of header data retrieval time.
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Mou Chin-Li
Soh Kap
Wang Chi-Lie
Yang Li-Jau
3Com Corporation
Bayard Djenane
Carpenter John W.
Reed Smith LLP
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