Patent
1995-08-17
1997-07-29
Swann, Tod R.
395471, G06F 1200
Patent
active
056528590
ABSTRACT:
A method and apparatus for snooping both cache memory and associated buffer queues in a cache subsystem arrangement. Since there are usually several requests for cache data being handled at any given time under high performance operation of multiple processors, a cache arrangement includes at least one buffer queue for storing the address of the cache data line and the status of the cache data line, which facilitate keeping track of the data requests and handling them efficiently. In response to a snoop request, a snoop address is compared to the address stored in the buffer queue so as to provide a positive comparison result if the snoop address matches the address stored in the buffer queue, thereby indicating a snoop hit condition. The buffer queue of the cache arrangement further has a snoop hit bit for storing a record of the positive comparison result that indicates the snoop hit condition. Even if there is still a pending transaction involving the buffer queue, the snoop request of the cache is satisfied once the comparison result has been stored in the snoop hit bit of the buffer queue, thereby keeping the cache high performance for local code while at the same time providing efficient support for snoop requests.
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Iacobovici Sorin
Mulla Dean
Institute for the Development of Emerging Architectures L.L.C.
King , Jr. Conley B.
Lenell Jack A.
Swann Tod R.
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