Method and apparatus for handling dynamic structural hazards and

Details Method and apparatus for handling dynamic structural hazards and Method and apparatus for handling dynamic structural hazards and

1997-12-30

1999-10-05

Treat, William M.

Electrical computers and digital processing systems: processing

Architecture based instruction processing

712214, 712215, 712 23, G06F 938

Patent

active

059616300

ABSTRACT:
A method for handling dynamic structural hazards and exceptions by using post-ready latency, including: receiving a plurality of instructions; selecting a first instruction whose execution can cause an exception; assigning a post-ready latency to a second instruction that follows the first instruction; and scheduling for execution the first instruction and the second instruction separated from the first instruction by an amount of time at least equal to the post-ready latency of the second instruction.

REFERENCES:
patent: 5555432 (1996-09-01), Hinton et al.
patent: 5655096 (1997-08-01), Branigin
patent: 5872948 (1999-02-01), Mallick et al.
patent: 5887174 (1999-03-01), Simons et al.

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