Method and apparatus for guaranteeing minimum variable schedule

Details Method and apparatus for guaranteeing minimum variable schedule Method and apparatus for guaranteeing minimum variable schedule

1997-12-30

1999-11-30

Treat, William M.

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

712214, 712215, G06F 938

Patent

active

059960647

ABSTRACT:
A method for guaranteeing minimum variable scheduling distance between instructions in a processor includes receiving a plurality of instructions and determining the post-ready latency of each instruction. Each instruction is then scheduled for execution so that the instruction follows an earlier instruction by an amount of time at least equal to the post-ready latency of the instruction.

REFERENCES:
patent: 5555432 (1996-09-01), Honton et al.
patent: 5590368 (1996-12-01), Heed et al.
patent: 5655096 (1997-08-01), Branigin
patent: 5771241 (1998-06-01), Brummel
patent: 5872948 (1999-02-01), Mallick et al.
patent: 5887174 (1999-03-01), Simons et al.

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