Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1999-02-09
2003-09-09
Ton, Dang (Department: 2666)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S429000, C370S235000
Reexamination Certificate
active
06618391
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to packet communication systems, and in particular to a method and an apparatus for scheduling packets in packet networks for guaranteeing data transfer rates to data sources and data transfer delays from data sources to destinations using a plurality of queues, each of the queues serving data connections with the same guaranteed data transfer rate, and only computing and sorting a single timestamp for each of the queues. This invention can be used in any system for data packet forwarding such as Asynchronous Transfer Mode (ATM) switches and Internet Protocol (IP) routers.
Per-Virtual-Connection (Per-VC) schedulers are known which aim to approximate a Generalized Processor Sharing policy, as described in A. K. Parekh and R. G. Gallager, “A Generalized Processor Sharing Approach to Flow Control in Integrated Services Networks: The Single-Node Case”, IEEE/ACM TRANSACTIONS ON NETWORKING, June 1993, pp. 344-357, which is incorporated herein by reference. As defined herein, the term “VC” is used throughout to mean “virtual connection”. It is understood that virtual connections may also include virtual circuits and Internet Protocol (IP) flows. Implementation of such Per-VC schedulers is a central issue in next-generation switching systems. In a market arena in which cost targets are precipitously dropping, an important objective is to minimize the complexity involved in Per-VC schedulers, and to minimize the cost differential with respect to switches using less sophisticated scheduling.
As defined herein and throughout, the term “GPS” is an abbreviation for the Generalized Processor Sharing policy, as described in A. K. Parekh et al., supra. GPS-related packet-scheduling disciplines are based on maintaining a global function, referred to by different authors either as a virtual time, such as in A. K. Parekh et al, supra, and in S. J. Golestani, “A Self-Clocked Fair Queuing Scheme for Broadband Applications”, PROCEEDINGS OF INFOCOM '94, April 1994, pp. 636-646, which is incorporated herein by reference; or as a system potential, such as described in D. Stiliadis and A. Varma, “Design and Analysis of Frame-based Fair Queuing: A New Traffic Scheduling Algorithm for Packet-Switched Networks”, PROCEEDINGS OF SIGMETRICS '96, May 1996, pp. 104-115; and D. Stiliadis and A. Varma, “Efficient Fair Queuing Algorithms for ATM and Packet Networks”, TECHNICAL REPORT UCSC-CRL-95-59, December 1995, with each of these references being incorporated herein by reference.
The global function tracks the amount of work that is done by the server to process packets in the communication system. The server uses this global function to compute, for each packet in the system, a timestamp that specifies when the packet should be transmitted relative to other packets. Packets are transmitted by increasing order of their timestamps. The specific function used as system potential determines the delay and fairness properties of each algorithm in the class.
The total implementation cost of these GPS-related scheduling algorithms is the combination of three factors: (i) the complexity of the function used as system potential to compute the timestamps for the packets in the system, (ii) the complexity involved in sorting the timestamps in order to select the packet with a minimum timestamp for transmission, and (iii) the cost of handling and storing the timestamps. In recent years, several scheduling algorithms which use a system-potential function of order
0
(
1
) complexity have been introduced. Examples of such algorithms include Self-Clocked Fair Queuing (SCFQ), as described in S. J. Golestani, supra; Frame-based Fair Queuing (FFQ), as described in D. Stiliadis et al., “Design and Analysis of Frame-based Fair Queuing . . . ”, supra; Virtual Clock, as described in L. Zhang, “Virtual Clock: A New Traffic Control Algorithm for Packet Switching”, ACM TRANSACTIONS ON COMPUTER SYSTEMS, May 1991, pp. 101-124; and Minimum-Delay Self-Clocked Fair Queuing (MD-SCFQ), described in F. M. Chiussi and A. Francini, “Minimum-Delay Self-Clocked Fair Queuing Algorithm for Packet-Switched Networks”, PROCEEDINGS OF INFOCOM '98, March 1998, each of which is incorporated herein by reference.
In particular, among these algorithms, MD-SCFQ has both optimal delay properties and excellent fairness properties. Scheduling algorithms achieving a desired performance with a system-potential function of minimal complexity are therefore available, but the total performance cost of the scheduler is still dominated by the complexity of sorting and storing the timestamps.
One well-known simplification in timestamp processing by a scheduler is obtained by assigning increasing values of timestamps to consecutive packets which belong to the same session, so that for each session only the timestamp of the packet at the head of the corresponding packet queue is to be considered and processed in the packet selection process. Such a timestamp is referred to as session timestamp. The number of session timestamps which have to be sorted is therefore equal to the number of sessions V supported by the scheduler. For example, typical values of V in current ATM switches, in which sessions are referred to as VCs, are in the order of tens of thousands of sessions. The range of possible values that the timestamps can assume at any given time depends on the ratio between the maximum and minimum service rates that the scheduler is required to provide to the connections. Such a timestamp range is typically very wide.
In view of the complexity in sorting a large number of timestamps over a wide range of possible values at the high speeds employed in broadband digital networks, hardware implementations of packet-switching systems are only affordable by data structures and processor configurations that are specifically devised to be efficiently mapped into silicon on integrated circuits or chips. Even with such specialized structures, the implementation cost may still be too high, and techniques to further reduce complexity are necessary. Different approaches are possible for this purpose. In some cases, the specific properties of a scheduler can help in simplifying the selection process.
Several techniques have been proposed to reduce the cost of the sorting operation. In particular, two approaches are the Logarithmic Calendar Queue (LCQ) introduced in F. M. Chiussi, A. Francini and J. G. Kneuer, “Implementing Fair Queuing in ATM Switches—Part 2: The Logarithmic Calendar Queue”, PROCEEDINGS OF GLOBECOM '97, November 1997, pp. 519-525; as well as the discrete-rate scheduler presented in J. C. R. Bennett, D. C. Stephens and H. Zhang, “High Speed, Scalable, and Accurate Implementation of Fair Queuing Algorithms in ATM Networks”, PROCEEDINGS OF ICNP '97, October 1997, pp. 7-14, each of which are incorporated herein by reference. Both of these approaches are arguably the two approaches that achieve the highest reduction in the hardware complexity of a GPS-related scheduler with optimal delay properties. In addition, such approaches introduce only a very small degradation in the delay bounds of the scheduler.
The LCQ is an optimized calendar queue which reduces the complexity by increasing, in an optimal manner, the granularity of the bins used to sort the timestamps, so that the relative degradation in delay bounds for each connection is equalized.
The discrete-rate scheduler is a relatively simple structure that can be used when the guaranteed service rates that the scheduler needs to support at any given time only belong to a relatively small set of discrete values. Such operating conditions are certainly realistic in most, if not all, ATM switches. As shown in
FIG. 1
, the illustrated discrete-rate scheduler 10 is a per-connection-timestamp scheduler having a corresponding timestamp for each of the sessions; for example, the sessions
14
-
16
in FIG.
1
. Each of the sessions
14
-
16
has a corresponding timestamp
20
-
26
, respectively.
Other advantages are known for using a discrete
Chiussi Fabio Massimo
Francini Andrea
Agere Systems Inc.
Ton Dang
Tran Phuc
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