Computer graphics processing and selective visual display system – Computer graphic processing system – Plural graphics processors
Reexamination Certificate
2002-12-13
2004-10-26
Chauhan, Ulka J. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphic processing system
Plural graphics processors
C345S426000, C345S506000, C345S520000, C345S522000, C717S136000, C719S320000, C719S321000
Reexamination Certificate
active
06809732
ABSTRACT:
BACKGROUND
1. Field of the Invention
The invention is in the field of computer graphics processor architecture and processing.
2. Description of Related Art
As is known by those skilled in the art of computer graphics, a computer typically comprises a general purpose processor that executes application program instructions and generates output data that is to be visually displayed on a monitor coupled to the computer. When performing computer graphics functions, the output data generated by the general purpose processor typically consists of a high level description of a scene for display, and other high level information such as from where the scene is to be viewed, what textures should be applied to different primitives in the scene, and where lights are located in the scene. However, the typical monitor is a simple device for accepting and outputting color information on a pixel-by-pixel basis; the typical monitor cannot interpret the output data from the application. Therefore, the output data must be processed by a graphics processor and translated into pixel color information for transmission to and display by the monitor.
A modern graphics processor frequently includes a fragment processor, also referred to as a pixel shader or pixel color processor. The fragment processor is primarily responsible for determining a final color for each fragment or pixel for which it receives information. For instance, such fragment information can include specular and diffuse lighting parameters, and texture information. However, in addition to fragment information, the fragment processor requires control information that specifies how the fragment processor is to process the fragment information to arrive at a final pixel color. The content of the control information depends on the type of fragment processor in use; one fragment processor can have a different number of computation units or computation units of a different type than another fragment processor, and would therefore require different control information or a different format of control information.
Graphics oriented Application Programming Interfaces (APIs), such as DirectX 8™ and OpenGL™, abstract these differences from application developers by providing a common set of commands that can be used to configure a variety of graphics processors. For instance, a version of DirectX 8 has 127 different commands available to application developers for control of a fragment processor in a graphics processor. An application developer can then arrange a sequence of commands chosen from these 127 commands, and present the sequence of commands to a driver written for the graphics processor in use. The driver converts the sequence of commands into a number of bits of control information that can directly configure the computation units of the graphics processor in use. Thus, the control information generated by the driver is specific to the architecture of the fragment processor in use and, therefore, the control information cannot be used to directly configure another type of fragment processor. This process of an application or a driver controlling a fragment processor by directly configuring its computation units with control information is known as state-based control of a fragment processor, and the information generated by the driver is known as state-based control information because the state (configuration) of computation units in the fragment processor is directly controlled by hardware or software external to the graphics processor. The set of control information active at a given time in a graphics processor is known in the art as “pipeline state”. Although the above-described method for controlling a fragment processor advanced the art of real-time creation of more realistic computer graphics, several limitations of state-based control methods are now evident.
One limitation is that the range of commands available for use by an application developer is inadequate for creating cutting edge computer graphics. Therefore, some application developers directly write state-based control information (created by the driver in the above example) because desired effects cannot be achieved using the commands available. Writing state-based control information is tedious, and the resulting state-based control information is likely to have errors. The resulting state-based control information is not portable to other fragment processors because the state-based control information comprehends characteristics of the fragment processor, such as the type, number, and arrangement of the fragment processor's resources.
An alternative approach is to provide application developers with a programmable fragment processor, which is programmed (controlled) by a shader program having a number of program instructions. Typically, for generating sophisticated graphics, controlling a fragment processor with program instructions is easier for an application developer than controlling a fragment processor with state-based control information because program instructions can be represented in a higher level programming language, and program instructions allow a greater range of operations than state-based control logic. Thus, a programmable fragment processor remedies some of the deficiencies of a state-based control fragment processor.
However, controlling a fragment processor with either program instructions or state-based control information still results in limitations. One limitation is that features of a newer fragment processor may go unused by an application written to use control information of a format compatible with an older fragment processor. Also, a programmer frequently develops a familiarity with a certain format of control information, and therefore has a preference to use that format of control information, rather than another format, when writing applications. Therefore, there is a need for a fragment processor that can use a variety of control information formats for controlling its computation units to process data.
SUMMARY
Embodiments of the invention receive control information in a plurality of formats and convert the control information into a native control format for controlling a programmable shader. In one embodiment, the invention comprises a state-based control translator for translating state-based control information into one or more codewords that natively control a programmable shader, and a program instruction translator for translating a program instruction into one or more codewords that natively control the programmable shader. Another embodiment comprises a programmable shader and a controller for detecting a start of a shader program and fetching one or more program instructions of the shader program, which are transmitted to the programmable shader. The programmable shader can begin to execute the program instructions fetched by the controller while the programmable shader fetches and translates other program instructions. Embodiments can use a memory register to store either state-based control information, if the programmable shader is to be controlled by state-based control information, or a program memory location reference identifying a memory location where one or more program instructions are stored, if the programmable shader is to be controlled by program instructions.
In one embodiment of the invention, a programmable shader for a graphics subsystem comprises a state-based control translator coupled to a data path, and configured to translate state-based control information into native control information and output the native control information to the data path. The programmer shader further comprises a program instruction translator coupled to the data path and configured to translate a program instruction into native control information and output the native control information to the data path, and a computation unit coupled to the data path to receive the native control information for configuration of the computation unit.
In another embodiment of the invention, a computing system, for proce
Feldman Zatz Harold Robert
Tannenbaum David C.
Chauhan Ulka J.
Moser, Patterson & Sheridon LLP
NVIDIA Corporation
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