Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
2005-02-22
2005-02-22
Paladini, Albert W. (Department: 2125)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C703S014000, C703S017000, C717S135000
Reexamination Certificate
active
06859770
ABSTRACT:
The present invention applies genetic algorithmic generation of test cases the simulation of VLSI logic circuit blocks. The present invention generates a number of original test cases. This aggregate of solutions is provided to a circuit simulator. The results of the simulator are maintained in a matrix or table. The results detail the number of times that particular logic states or events associated with the VLSI block have been stimulated by particular test cases. The aggregate of solutions and the simulation results are then analyzed by the genetic algorithm. The genetic algorithm preferably identifies states associated with the circuit simulation that have not been produced by the original test cases. The genetic algorithm then combines characteristics of various test cases to generate new test cases. The new test cases are provided to the circuit simulator thereby providing a higher degree of confidence that the entire VLSI chip design has been simulated.
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“Statistical Modeling for Efficient Parametric Yield Estimation of MOS VLSI Circuits” Paul Cox et al., IEEE Trans. Electron. Devices, vol. ED-32 No. 2, pp. 471-478, 1985.
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