Method and apparatus for generating timing pulses accurately ske

Details Method and apparatus for generating timing pulses accurately ske Method and apparatus for generating timing pulses accurately ske

1995-09-29

1998-06-16

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327158, 327233, 326 93, 365233, H03K 5135, G11C 804

Patent

active

057677158

ABSTRACT:
The timing signal output from a subject circuit is accurately skewed relative to a base clock signal period. A phase-locked loop ("PLL") and sample delay circuit are implemented with the subject circuit. The PLL receives the base clock signal and generates a local clock signal. The local clock signal is input to a sample delay circuit and the subject circuit. The sample circuit generates a delay approximating that of the subject circuit. The output of the sample delay circuit is fed back into the PLL. With the base clock as the PLL's reference signal and the delayed signal as the feedback signal, the local clock signal phase is forced to precede the base clock phase by the propagation delay of the sample delay circuit. In effect, the propagation delay is nulled out. For a PLL generating multiple output phases a zero phase goes to the sample delay circuit and an output with a phase corresponding to a desired skew goes to the subject circuit. Also, a class of logic devices is defined in which propagation delays are nulled out.

REFERENCES:
patent: 5517147 (1996-05-01), Burroughs et al.
patent: 5578945 (1996-11-01), Flora
F. Lee and P. Pun, Application Note (Preliminary) Phase-Locked Loops, LSI Logic, Sep. 20, 1990, pp. 1-17.
"0.5 .mu.m Technology PLL Phase-Locked Loop Macrofunction Family," Oki Semiconductor Data Sheet, Oct. 1994, pp. 1-13.
Johnson et al., "A Variable Delay Line PLL for CPU-Coprocessor Synchronization;" IEEE Journal of Solid-State Circuits, vol. Synchronization; IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988.

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