Pulse or digital communications – Synchronizers
Reexamination Certificate
2006-02-28
2010-11-02
Liu, Shuwang (Department: 2611)
Pulse or digital communications
Synchronizers
C375S357000, C375S362000, C375S365000, C375S368000, C375S371000, C375S373000, C375S376000
Reexamination Certificate
active
07826579
ABSTRACT:
A clock generator circuit for generating synchronization signals for a multiple chip system. The clock generator circuit comprises generation of a synchronization signal from a reference clock and chip global clock with edge detection logic. In high performance server system design with multiple chips, a common practice for server systems is to use feedback clock and delayed reference clock to generate the synchronization signal. The generated synchronization signal is transferred to latches clocked by the global clock to be used for chip synchronization functions. As the system clock frequency is pushed higher, the phase difference between generated synchronization signal clocked by feedback clock and receiving latch clocked by global clock is becoming such a large portion of cycle time that this signal cannot be transferred deterministically. This invention resolves the uncertainty problem and allows the synchronization signals to be generated deterministically independent of the chip global clock cycle time.
REFERENCES:
patent: 5850414 (1998-12-01), Miyajima
patent: 6665359 (2003-12-01), Flake
patent: 6792554 (2004-09-01), Gervais et al.
patent: 6819726 (2004-11-01), Drerup et al.
patent: 2003/0091137 (2003-05-01), Vallet et al.
Becker Wiren D.
Hwang Charlie C.
McNamara Timothy G.
Tong Ching-Lung
Cantor & Colburn LLP
International Business Machines - Corporation
Kinnaman, Jr. William
Liu Shuwang
Patel Dhaval
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