Method and apparatus for generating sign-digit format of sum...

Details Method and apparatus for generating sign-digit format of sum... Method and apparatus for generating sign-digit format of sum...

2007-01-02

2007-01-02

Malzahn, D. H. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

10371272

ABSTRACT:
A system and method for converting two binary digits into redundant sign-digit format. The system comprises a first adder for adding the binary digits together to generate a first result. A second adder adds an input carry from a previous digit to the first result and subtracts a value equal to the radix of the of the binary digits form the first result if the first result is greater than an initial threshold in order to generate an intermediate result. The system further includes a third adder for adding a second input carry from the previous digit to the intermediate result and subtracting the value of the radix from the intermediate result if the intermediate result is greater than a prescribed value such that the addition of the two binary digits are in redundant sign-digit format.

REFERENCES:
patent: 5113363 (1992-05-01), Orsino et al.
patent: 6754689 (2004-06-01), Bhushan et al.
patent: 2001/0016865 (2001-08-01), Goto

Affiliated with

Also associated with

Rating

Method and apparatus for generating sign-digit format of sum... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for generating sign-digit format of sum..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for generating sign-digit format of sum... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3752132