Method and apparatus for generating Reed-Soloman error correctin

Details Method and apparatus for generating Reed-Soloman error correctin Method and apparatus for generating Reed-Soloman error correctin

1992-03-25

1994-12-20

Beausoliel, Jr., Robert W.

Excavating

371 375, 371 376, H03M 1300, G06F 1100

Patent

active

053751272

ABSTRACT:
An error correction code (ECC) generator/checker for processing high bandwidth data block transfers. The high bandwidth ECC generator/checker logic includes a plurality stages, each stage including Reed-Solomon Cyclic Redundancy Check (RS CRC) code logic for processing a single data word. The stages can be configured to operate in parallel to process multiple-word parallel, high bandwidth transfers, or individually wherein each stage processes data in a word-serial manner. Each stage includes a first input for receiving a respective word portion of a multiple-word transfer, a second input for receiving either an intermediate ECC value from a previous stage or a feed back value, means for combining data words received at the first and second inputs, an alpha multiplier and an output for providing an ECC word.
When configured to operate in high bandwidth mode the output of the stages are connected in series such that the first stage output is connected to the second input of the second stage, the second stage output is connected to the second input of the third stage, and so on. The output of the final stage is fed back to the second input of the first stage. When configured to operate in a word-serial manner, the output for each stage is fed back to its second input.

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