Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2006-05-12
2009-02-10
Luu, Pho M. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185240, C365S189090, C365S211000, C365S230060
Reexamination Certificate
active
07489556
ABSTRACT:
Method and apparatus for generating a word-line voltage are disclosed. A word-line voltage generator includes a first current source, an adjustable current source, and a voltage converter, all operably coupled to a current sum node. The first current source generates a first current wherein a voltage derived from the first current at least partially comprises a cell location-dependent temperature coefficient varying with a location of a memory cell in a string of interconnected bit cells. The adjustable current source generates a second current that is substantially independent of a temperature change. The voltage converter is configured for generating a word-line signal having a word-line voltage proportional to the first current.
REFERENCES:
patent: 5229711 (1993-07-01), Inoue
patent: 5377156 (1994-12-01), Watanabe et al.
patent: 5539690 (1996-07-01), Talreja et al.
patent: 5581504 (1996-12-01), Chang
patent: 5673223 (1997-09-01), Park
patent: 5734609 (1998-03-01), Choi et al.
patent: 5828611 (1998-10-01), Kaneko et al.
patent: 5864504 (1999-01-01), Tanzawa et al.
patent: 5912489 (1999-06-01), Chen et al.
patent: 6009014 (1999-12-01), Hollmer et al.
patent: 6018235 (2000-01-01), Mikuni
patent: 6046944 (2000-04-01), Singh
patent: 6147914 (2000-11-01), Leung et al.
patent: 6175522 (2001-01-01), Fang
patent: 6255900 (2001-07-01), Chang et al.
patent: 6281743 (2001-08-01), Doyle
patent: 6323630 (2001-11-01), Banba
patent: 6330195 (2001-12-01), Marr
patent: 6377090 (2002-04-01), Bruno
patent: 6452437 (2002-09-01), Takeuchi et al.
patent: 6489835 (2002-12-01), Yu et al.
patent: 6489836 (2002-12-01), Yeong
patent: 6556478 (2003-04-01), Willis et al.
patent: 6559629 (2003-05-01), Fernald
patent: 6567302 (2003-05-01), Lakhani
patent: 6603702 (2003-08-01), Kojima
patent: 6642778 (2003-11-01), Opris
patent: 6650567 (2003-11-01), Cho et al.
patent: 6667904 (2003-12-01), Takeuchi et al.
patent: 6683481 (2004-01-01), Zhou et al.
patent: 6693843 (2004-02-01), Maffitt et al.
patent: 6714455 (2004-03-01), Banks
patent: 6738290 (2004-05-01), Lee et al.
patent: 6744676 (2004-06-01), Leung et al.
patent: 6801454 (2004-10-01), Wang et al.
patent: 6847240 (2005-01-01), Zhou
patent: 6853238 (2005-02-01), Dempsey et al.
patent: 6870766 (2005-03-01), Cho et al.
patent: 6934209 (2005-08-01), Marr
patent: 6954394 (2005-10-01), Knall et al.
patent: 6975542 (2005-12-01), Roohparvar
patent: 7005839 (2006-02-01), Wada
patent: 7034514 (2006-04-01), Tachibana et al.
patent: 7072238 (2006-07-01), Chae et al.
patent: 7113025 (2006-09-01), Washburn
patent: 7119528 (2006-10-01), Rasmus
patent: 7149132 (2006-12-01), Bedeschi et al.
patent: 7164604 (2007-01-01), Arakawa
patent: 7274250 (2007-09-01), Hazucha et al.
patent: 7277355 (2007-10-01), Tanzawa
patent: 2002/0085429 (2002-07-01), Kim et al.
patent: 2004/0130938 (2004-07-01), Hamaguchi
patent: 2005/0078518 (2005-04-01), Nguyen
patent: 2005/0122779 (2005-06-01), Fasoli et al.
patent: 2005/0134345 (2005-06-01), McClure
patent: 2006/0023505 (2006-02-01), Iizuka
patent: 2008/0025121 (2008-01-01), Tanzawa
Banba et al., “A CMOS Band-Gap Reference Circuit with Sub IV Operation,” Symposium on VLSI Circuits, Digest of Technical Papers, 228-229 (1998).
Banba et al., “A CMOS Bandgap Reference Circuit with Sub-1-V Operation,” IEEE Journal of Solid-State Circuits, 670-674 (1999).
Kuijk, Karel E., “A Precision Reference Voltage Source,” IEEE Journal of Solid-State Circuits, 222-226 (1973).
Nozoe et al., “A 256-Mb Multilevel Flash Memory with 2-MB/s Program Rate for Mass Storage Applications,” IEEE Journal of Solid-State Circuits, 1544-1550 (1999).
Nozoe et al., “A 256Mb Multilevel Flash Memory with 2MB/s Program Rate for Mass Storage Applications,” IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 110-111, 451 (1999).
Pierazzi et al., “Band-Gap References for Near I-V Operation in Standard CMOS Technology,” IEEE Custom Integrated Circuits Conference, 463-466 (2001).
Ripamonti et al., “Low Power-Low Voltage Band Gap References for FLASH-EEPROM Integrated Circuits: Design Alternatives and Experiments,” IEEE, 635-638 (1999).
Tanzawa et al., “Wordline Voltage Generating System for Low-Power Low-Voltage Flash Memories,” IEEE Journal of Solid-State Circuits, 55-63 (2001).
Yen et al., “A Precision CMOS Power-On-Reset Circuit with Power Noise Immunity for Low-Voltage Technology,” IEICE Trans. Electron, 778-784 (2004).
Luu Pho M.
Micro)n Technology, Inc.
TraskBritt
LandOfFree
Method and apparatus for generating read and verify... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for generating read and verify..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for generating read and verify... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4102345