Method and apparatus for generating phase locked digital clock s

Details Method and apparatus for generating phase locked digital clock s Method and apparatus for generating phase locked digital clock s

1983-04-29

1985-12-31

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307262, 307269, 328155, 377108, H03K 117, H03K 513, H03K 2136

Patent

active

045624020

ABSTRACT:
A method and apparatus for generating two phase locked digital clocks of different word rates particularly suited for a graphic and alphanumeric computer display terminal. Master and slave clock generators are used to generate output pulses at every N-th and M-th clocks of a common clock. A phase lock loop including the master clock generator and a phase lock counter dividing the common clock by the factor of the least common multiple of N and M is used to synchronize the slave clock generator.

REFERENCES:
patent: 4423383 (1983-12-01), Svendsen

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