Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1998-09-04
2002-04-30
Vu, Huy D. (Department: 2663)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S469000
Reexamination Certificate
active
06381245
ABSTRACT:
BACKGROUND OF THE INVENTION
Asynchronous transfer mode (ATM) communication systems are widely used for network communications. In general, ATM communication protocols involve logical stacks having several layers including a physical layer as the lowest layer. The ATM physical layer typically involves the movement of cells between source and target physical layer devices. The cells are often moved across a bus in smaller parallel sets of data. When the data reaches the target device, the cell is reconstructed and then sent up the stack to its final destination.
One example of an ATM physical layer protocol is the UTOPIA
2
protocol. Devices can use UTOPIA
2
protocol and a UTOPIA
2
bus to move data between the physical layer and an ATM layer device. An ATM layer device can comprise, for example, a UTOPIA
2
master device. In UTOPIA
2
protocol, data is moved from an initial physical layer device, to a UTOPIA
2
master device, and then to a target device. In such a protocol, the UTOPIA
2
master can check for parity on the data received by the UTOPIA
2
master. However, some physical layer devices do not have the ability to generate parity for the transmitted data.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method and apparatus for generating parity for communication between a physical layer device and an ATM layer device is disclosed that provides significant advantages over prior developed systems.
According to one aspect of the present invention, a method for generating parity for data transmitted between a physical layer device and an ATM layer device is provided. The method comprises monitoring a data bus for data comprising an ATM cell transmitted from a physical layer device to an ATM layer device. The method further comprises verifying the header error check of the ATM cell, generating parity for the ATM cell, and providing the parity to the ATM layer device if the header error check is correct.
In one embodiment, the method also includes monitoring an address bus to identify that the physical layer device requires parity to be generated.
In another embodiment, the method further includes setting an error signal if the header error check is incorrect.
According to another aspect of the present invention, an apparatus is provided for generating parity for data transmitted between a physical layer device and an ATM layer device. The apparatus comprises an interface coupled to a data bus. The interface is operable to monitor the data bus for data comprising an ATM cell transmitted from a physical layer device to an ATM layer device. The apparatus further comprises a controller coupled to the interface. The controller is operable to verify the header error check of the ATM cell and generate parity for the ATM cell. A parity output is coupled between the controller and the ATM layer device. The parity output can provide the parity to the ATM layer device if the header error check is correct.
It is a technical advantage of the present invention that it provides parity for physical layer devices that do not have the capability to generate parity when communicating with an ATM layer device.
It is a further technical advantage of the present invention that it provides an additional path integrity check for data communicated between physical layer devices and an ATM layer device.
Other technical advantages should be apparent to one of ordinary skill in the art in view of the specification, claims, and drawings.
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Brewer William Keith
Hann William Patrick
House Richard L.
Irvin Matthew G.
Baker & Botts L.L.P.
Mehra Inder
Vu Huy D.
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