Method and apparatus for generating one or more clock...

Details Method and apparatus for generating one or more clock... Method and apparatus for generating one or more clock...

2006-02-17

2009-11-10

Kim, Kevin Y (Department: 2611)

Pulse or digital communications

Equalizers

Automatic

Reexamination Certificate

active

07616686

ABSTRACT:
Methods and apparatus are provided for generating one or more clock signals for a decision-feedback equalizer using DFE detected data. A received signal is sampled using a data clock and a transition clock to generate a data sample signal and a transition sample signal, respectively. A DFE correction is obtained for each of the data sample and transition sample signals to generate DFE detected data and a DFE transition data. The DFE detected data and DFE transition data are then applied to a phase detector that generates a signal to adjust a phase of one or more of the data clock and transition clock. In a multi-level implementation, the received signal is sampled using a clock associated with each of the levels and the samples are latched using a vertical slicing technique to generate DFE data associated with each of said levels.

REFERENCES:
Stojanovic et al., “Autonomous Dual-Mode (PAM2/4) Serial Link Transceiver with Adaptive Equalization and Data Recovery,” IEEE Journal of Solid-State Circuits, vol. 40, No. 4, pp. 1012-1026 (Apr. 2005).

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