Method and apparatus for generating memory addresses for testing

Details Method and apparatus for generating memory addresses for testing Method and apparatus for generating memory addresses for testing

1998-05-22

2000-04-11

Nelms, David

Static information storage and retrieval

Addressing

Counting

365201, G11C 800, G11C 700

Patent

active

060495057

ABSTRACT:
A counter internal to a memory device for generating memory addresses in physical or logical sequence in non-redundant or redundant memory space, counting up or down in increments of the user's choice. The counter may be advantageously used to generate memory addresses for functional testing of the memory cells within the memory device.

REFERENCES:
patent: 5390149 (1995-02-01), Vogley et al.
patent: 5410687 (1995-04-01), Fujisaki et al.
patent: 5777921 (1998-07-01), Tasaka et al.
patent: 5818772 (1998-10-01), Kuge

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