Excavating
Patent
1996-06-04
1997-07-08
Canney, Vincent P.
Excavating
G06F 1100
Patent
active
056469497
ABSTRACT:
An apparatus and method for generating pseudo-random test instructions for testing a microprocessor begins by providing an array of list structures (502 through 508). Each list structure (502 through 508) contains a list of instructions, a discipline field (34), a pick field (42) and a biasing field (36). A random list of instructions is created by using a list selection discipline field to determine which list (502 through 508) is selected. The discipline field in the particular list (502 through 508) is then used to determine a manner in which instructions are selected from a list of instructions contained within the list structure. The pick field indicates how many instructions are to be selected from each selected list structure using a method determined via the discipline field. Once a number of instructions equal to the pick value has been selected, another list structure is selected as determined in the list selection discipline field until an entire test file of computer instructions is fully generated.
REFERENCES:
patent: 5570376 (1996-10-01), Kunda et al.
"Verification of the IBM RISC System/6000 By A Dynamic Biased Pseudo-Random Test Program Generator," A. Aharon et al.; IBM Systems Journal, vol. 30, No. 4, 1991; pp. 527-537.
"RTPG-A Dynamic Biased Pseudo-Random Test Program Generator for Processor Verification," A. Aharon et al.; IBM Science and Technology Technical Report 88.290, Jul. 1990.
Bruce, Jr. William C.
Laurens Judith Elizabeth
Law Wai-on
Rudnick Elizabeth Marie
Canney Vincent P.
Motorola Inc.
Witek Keith E.
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