Method and apparatus for generating frequency divided signals

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Frequency or repetition rate conversion or control

Reexamination Certificate

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Details

C327S117000, C327S202000, C377S047000, C377S048000

Reexamination Certificate

active

08030975

ABSTRACT:
A frequency divider includes a first frequency divider stage coupled to a clock signal and operative to generate a first frequency divided signal. A second frequency divider stage is coupled to the clock signal and to the first frequency divider stage and is operative to generate a second frequency divided signal. A third frequency divider stage is coupled to the clock signal and to the second frequency divider stage and is configured to generate a third frequency divided signal using only i) the clock signal and ii) the second frequency divided signal so that any transition of the third frequency divided signal occurs at an edge of the clock signal at which the second frequency divided signal does not transition.

REFERENCES:
patent: 6249157 (2001-06-01), Nakura et al.
patent: 6961403 (2005-11-01), Austin et al.
patent: 7149275 (2006-12-01), Hubbard
patent: 2003/0053385 (2003-03-01), Tobita et al.
patent: 2006/0273833 (2006-12-01), Chen
Wikipedia—Clock Edge http://en.wikipedia.org/wiki/Clock—edge.

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