Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating
Reexamination Certificate
1998-10-27
2001-09-11
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Clock or pulse waveform generating
C327S292000, C327S293000
Reexamination Certificate
active
06288589
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices. More specifically, the present invention relates to the synchronization of logic within a semiconductor device.
2. Description of the Related Art
Clocking in Digital Logic
The Purpose of Clocks;
Clocks are periodic signals used for timing and synchronization purposes in synchronous digital logic. Clocks define periods of time in which logic operations are performed by circuits. Logic operations involve the propagation of state through a series of logic gates.
In synchronous circuits logic state propagation is launched or initiated by a source clock edge. After propagating through paths of logic gates, the resulting logic state is sampled by a destination clock edge. The destination clock edge is generated from a clock event that follows the clock event that generated the source clock edge.
Since propagation of state through paths of gates takes time, for some period of time after the source clock edge, logic paths will contain state that is new (or valid for this cycle) and state that is old (invalid for this cycle). Generally, at the end of a period of time (often defined as a clock cycle), valid state has propagated through the entire path or collection of paths and there is no longer any invalid state in the circuit. The following clock edge starts the process anew.
Logical operations as implemented in electronic circuits propagate through paths of logic gates that diverge and converge. When logic paths converge or are combined with other paths they must do so at a similar point in time—this is the time at which the various convergent paths all have valid data. This point of time is determined by the arrival time of the latest arriving data. There are generally other, faster paths converging on this point that must hold their valid data until it has been successfully combined with the late-arriving data. In most digital circuits, the clock or clocks provide this synchronization function. Thus, clocks can be thought of as performing a regulating or governing function—they slow down or hold faster paths until the slower paths have become valid.
Generally speaking, it is required that logic circuits work as quickly as possible. It is therefore highly desirable that the clocks perform their regulating function while imposing as little penalty as possible on the operating speed of the circuit.
Clock Skew
Clock skew is a component of timing error that can both interfere with the regulating function of the clocks and reduce the maximum operating speed of the circuit. The definition of clock skew is that it is the difference in arrival times among clock edges that are derived from the same clock event but are associated with physically distinct clock nodes.
For example, a master clock is commonly distributed by some means to a large number of destinations. The distribution means may be as simple as a network of wires or may include many levels of active buffers.
FIG.1
illustrates a clock system with a single clock source (typically a phase locked loop, a PLL, or a digital delay loop, a DLL) followed by some number of generators. The generators reshape the single clock source into multiple clocks. The reshaping that occurs in a generator can be either a straightforward delay of the source clock, it can be an inversion of the source clock, or it can be a change of the shape of the clock waveform (e.g., change in duty cycle, change in slew rate, etc.) Or it can also be any combination of the previous transformations. In any case, the propagation time of a clock edge through this distribution path requires some non-zero time. The propagation time to each destination can be tuned by design to be smaller or larger according to the needs of the design. In practice it is expensive (in terms of design effort) to analyze or model the clock distribution circuit so as to predict actual clock skew with total accuracy.
Actually, even with perfect design knowledge it is impossible to control skew with total accuracy because of normal manufacturing variations across a circuit. For example, a certain clock distribution wire may be somewhat more resistive in part of the circuit due to localized variations in interconnect thickness or width. This could result in a consistently longer delay to the clock destination at the end of this wire relative to other clock destinations on a particular die
It can be seen then that clock skew has both predictable and unpredictable components. With some degree of difficulty, the designer can adjust or control clock skew within certain limits. In practice, this control is limited by the available design time and also by normal manufacturing or environmental variations. As a result of the difficulty in perfectly controlling clock skew and because of the detrimental effects of clock skew, it is important that a design be tolerant of some uncertainty in clock skew among the various clock destinations.
Clock Jitter
Like clock skew, clock jitter is a component of timing error that can adversely affect the regulating function of the clock and also the operating speed of the circuit. Clock jitter is defined to be the error or variation in arrival time of a clock event on a single clock node. This error or variation is relative to an ideal or intended arrival time, usually specified with respect to an immediately prior clock event. Thus, while clock skew describes arrival times of the same event at physically separate locations, clock jitter describes arrival times of different events at the same physical location. Clock jitter may be somewhat different at each clock node.
Clock jitter is rarely if ever intentionally introduced into a clock network (one exception is intentional frequency modulation of the clock). Jitter can be caused by several factors. Jitter may be present on the input clock of the circuit. This generally is passed along through the distribution network. Additionally, it may be introduced by part of the clock generation logic such as a PLL. For example,
FIG. 4
illustrates the introduction of jitter by the clock generation logic, which shows a feedback-base control system (a typical PLL) coupling to a transfer function of Z(s) (the clock generator). The PLL contains a steady state phase error that affects edge placement. Noise injected into the system at various points will cause transient responses in the system. Noise can occur in the reference signal &thgr;(t), the phase comparator, the loop filter, the voltage controlled oscillator (VCO), the clock generator (Z(s)), or on any of the wires connecting the components. For these components, the primary source of noise is the voltage sources (power and ground), and for the wires, it is coupling noise.
Clock jitter can also be caused by power supply noise and by inductive or capacitive signal coupling. The effect of jitter is to shorten or lengthen clock periods as perceived by certain parts of the circuit. For example, if a certain clock edge is delayed from the arrival time predicted by the prior edge, the ending clock period is lengthened while the following clock period is likely shortened.
Clock jitter that varies among various clock destinations can also increase clock skew. For example, local supply noise may cause a clock edge to arrive early in one location while the same clock edge may arrive on time at another location.
Clock jitter may be short term, causing a cycle to cycle variation in the clock period, or may be longer term, affecting a series of sequential cycles in a similar way. Jitter may also cause the duty cycle of a clock to vary from its intended value. There are usually both short and long term components of jitter present in a clock.
Setup and Hold Hazards
Setup and hold time hazards could exist even with no clock skew or jitter, but skew (especially unpredictable skew) and jitter generally increase the likelihood and severity of these hazards. A setup hazard occurs when a clock edge is sampling data that is arriving very late relative to the clock. If the data is too la
Blomgren James S.
Horne Stephen C.
Petro Anthony M.
Potter Terence M.
Booth Matthew J.
Booth & Wright, L.L.P.
Cunningham Terry D.
Intrinsity, Inc.
Tra Quan
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