Method and apparatus for generating carries in an adder circuit

Details Method and apparatus for generating carries in an adder circuit Method and apparatus for generating carries in an adder circuit

1997-05-05

1999-08-31

Malzahn, David H.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

G06F 750

Patent

active

059447770

ABSTRACT:
An adder circuit to generate carry-outs and a method implemented by the adder circuit. First and second groups of consecutive group generate terms are calculated. The first group of group generate terms are combined to calculate a first result at a first logic level, and the second group of group generate terms are combined to calculate a second result at the same logic level. The first and second results are then combined to calculate a carry-out at a second logic level.

REFERENCES:
patent: 4163211 (1979-07-01), Miura
patent: 4504924 (1985-03-01), Cook et al.
patent: 4660165 (1987-04-01), Masumoto
patent: 4764886 (1988-08-01), Yano
patent: 5095458 (1992-03-01), Lynch et al.
patent: 5122982 (1992-06-01), Cohn
patent: 5479356 (1995-12-01), Shackleford et al.

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