Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data
Reexamination Certificate
2007-01-23
2007-01-23
Kim, Kevin (Department: 2611)
Pulse or digital communications
Synchronizers
Synchronizing the sampling time of digital data
Reexamination Certificate
active
10133609
ABSTRACT:
A timing estimation mechanism operative to generate an oversampling clock signal for a large range of reference clock frequencies without requiring use of a PLL. The oversampling timing mechanism generates appropriate timing instances, typically for the purpose of sampling a received data signal in a digital communications system, without requiring a specific external clock source but rather by utilizing a clock source having any arbitrary frequency. The mechanism of the present invention is especially suited for use in applications where a specific external clock source (e.g., integer multiple of the data rate) is not available and wherein the implications of the use of a PLL cannot be tolerated. The oversampling clock estimation mechanism generates a clock signal which may be unevenly distributed over the symbol period, but whereby on average, the correct number of samples is produced over a specific time duration.
REFERENCES:
patent: 5454007 (1995-09-01), Dutta
patent: 6249555 (2001-06-01), Rainbolt
patent: 6985819 (2006-01-01), Lipscomb et al.
patent: 2004/0077319 (2004-04-01), Koike et al.
Bronfer Alexander
Isaac Ronen
Suissa Udi
Brady III W. James
Kim Kevin
Neerings Ronald O.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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