Method and apparatus for generating a zero bit status flag in a

Boots – shoes – and leggings

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

36471503, 364749, G06F 700, G06F 738

Patent

active

056383126

ABSTRACT:
A method and apparatus for generating a zero flag (z-flag) status signal in a microprocessor includes a z-flag signal generator that generates a z-flag signal from unaligned data simultaneous to the load alignment of such data. The z-flag generator first performs a zero detect on each byte of data retrieved from memory. The zero detect results are next decoded according to bit selection signals generated from a data format code which corresponds to the specific format of the retrieved data.

REFERENCES:
patent: 4323981 (1982-04-01), Nakamura
patent: 5469377 (1995-11-01), Amano

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method and apparatus for generating a zero bit status flag in a does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for generating a zero bit status flag in a , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for generating a zero bit status flag in a will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-770402

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.