Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Reexamination Certificate
1999-08-02
2001-05-08
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Having specific delay in producing output waveform
C327S269000, C327S270000
Reexamination Certificate
active
06229367
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to generation of intentional time delays into incoming signals.
2. Description of the Related Art
A conventional time delay system in shown in
FIG. 1
a.
The time delay system
40
includes a series/parallel combination of buffers
12
,
16
,
18
,
22
,
24
,
26
,
28
,
32
through
34
and multiplexers
14
,
20
,
30
, and
36
. The time delay system
40
also includes delay control bits S
0
-S
3
. Each of the buffers
12
,
16
,
18
,
22
,
24
,
26
,
28
,
32
through
34
is a delay element that provides a time delay into its input signal. The delay control bits S
0
-S
3
control multiplexers
14
,
20
,
30
, and
36
so that the multiplexers select either signals or non-delayed signals. For instance if S
0
is 0, then the multiplexer
14
chooses the non-delayed input signal at a node
10
rather than the input-signal delayed by the time delayed associated with the buffer
12
. In operation, if the delay control bits S
0
-S
3
are 1100, then the output signal
38
is the input signal
10
delayed by the time delay of the buffers
12
,
16
, and
18
and the intrinsic time delay associated with the multiplexers
14
,
20
,
30
, and
36
.
Another known approach is illustrated conceptually in
FIG. 14
a.
This scheme provides the same functionality as the approach in
FIG. 1
, but it eliminates the concatenation of multiple multiplexers. A third known approach shown in
FIG. 14
b
is to use a resistive ladder to delay the incoming signal based on an RC time constant. As the values of resistors
1041
,
1043
,
1045
and
1047
are increased by linear multiples of some value R, and the value C is the same for capacitors
1048
, the delay step &tgr;
delta
produced by the ladder equals &tgr;
RC
.
The two approaches of
FIGS. 14
a
and
14
b
can be combined such that the output
1044
of the time delay system of
FIG. 14
a
is coupled to the input node
1049
of the time-delay system of
FIG. 14
b,
wherein the time delay system of
FIG. 14
a
acts as a coarse vernier and the time delay system of
FIG. 14
b
acts as a fine adjustment.
Another well-known technique is illustrated in
FIG. 15
a,
wherein a voltage
1054
through resistor R is connected to an integrator formed by capacitor
1056
and amplifier
1058
at a known time t corresponding to the rising edge of an input signal to be delayed. The voltage at the output of the integrator is a ramping voltage which is quite linear and which has a duration equal to the delay range of the circuit. The ramp voltage is input to one input of a comparator circuit
1060
. The other input of comparator
1060
is coupled to the output of a digital-to-analog converter (DAC)
1062
. The DAC
1062
produces a voltage which is linearly proportional to the n-bit digital program work presented on DAC input
1064
.
When the ramp voltage hits the same voltage level as that which is output by the DAC
1062
, the comparator switches and produces an edge which is delayed by the amount of time it took for the ramp to reach the DAC voltage level.
One application of the conventional time delay system or the present invention is in generating deskew delays for a random access memory (RAM) tester as shown in
FIG. 1
b.
A timing generator
46
provides test signals to the test devices such as RAM
1
, RAM
2
, and RAM N. The test devices RAMs
1
-N are connected to the timing generator
46
through cables
1
-N. Because the cables
1
-N are different in length, the signals sent by the timing generator
46
arrive at the test devices RAMs
1
-N at difference times. In order to have the signals arrive at the test devices RAMs
1
-N at the same time, deskew delay units
1
-N may be provided as shown in
FIG. 1
b.
Each of the deskew delay units
1
-N may incorporate the time delay system
40
or the present invention which is programmed to provide a time delay so that all of the test devices RAMs
1
-N receive the signals from the timing generator
46
at the same time.
One problem associated with the conventional time delay systems is the data dependency error. A data dependency error is described with reference to
FIG. 2. A
time delay system
51
in
FIG. 2
consists of four delay elements including buffers
52
,
54
,
56
, and
58
. An input signal
50
a
at an input node
50
has a repetition period of T
p
. A first pulse
50
b
of the input signal
50
a
travels through the buffers
52
,
54
,
56
, and
58
, and reaches an output node
60
after a time delay Td
1
. A second pulse
50
c
of the input signal
50
a
reaches the output
60
after a time delay of Td
2
. A data dependency error is defined as Td
2
-Td
1
. Ideally, Td
1
should be equal to Td
2
. In such a case, the data dependency error is zero. Typically, a data dependency error is not zero. As the repetition rate T
p
decreases, the substrate settling time increases, the data dependency error becomes worse. The substrate settling time will be described in more detail with reference to FIG.
8
. In addition, as the required time delay becomes longer, the data dependency error of a delayed signal of a conventional time delay system increases. For example, to provide a long time delay, the time delay system
40
requires more buffers. As more buffers are added, the data dependency error also increases. At some point, the data dependency error may become too large to be acceptable especially for highly accurate timing systems.
Accordingly, there is a need for a time delay system that can provide a minimum data dependency error that is independent of the repetition rate of the input signal, the substrate settling time, and the length of the time delay.
SUMMARY OF THE INVENTION
The present invention provides a time delay system that generates a selectable asynchronous time delayed signal from an incoming signal using a pulse having a minimum pulse width and a stop-startable oscillator. The time delay system of the present invention produces a minimum data dependency error which is independent of the repetition rate of the incoming signal, the substrate settling time, and the length of the time delay of the delayed signal.
By stopping and re-starting the oscillator only for a short duration in response to the short pulse that has a known phase with respect to the incoming signal, the phase of the oscillator is aligned to the incoming signal, the oscillator period does not change with the repetition rate of the incoming signal, and the oscillator's substrate receives minimum perturbation. Hence, the oscillator introduces only an insignificant amount of data dependency error, and the time delay system of the present invention can generate a delayed signal having even a very long time delay.
The time delay system of the present invention may include a pulse generator for generating a short pulse in response to an input pulse, a stop-startable oscillator for generating multiple oscillating signals capable of providing multiple steps of a medium-sized time delay, where the oscillator is stopped in response to the leading edge of the short pulse and re-started in response to the trailing edge of the short pulse.
The time delay system may further include a multiplexer for selecting one of the oscillating signals, a vernier for providing multiple steps of a fine time delay, and a shift register for providing multiple steps of a coarse time delay, where a step of the medium-sized time delay is typically greater than a step of the fine time delay, and a step of the coarse time delay is typically one period of the oscillator. A total fine time delay which is a sum of all of the steps of the fine time delay is typically greater than a step of the medium-sized time delay so that there is no discontinuity from one time delay step to the next.
The time delay system may also include a pipeline unit for delivering the short pulse to the shift register at a time appropriate for the amount of time delay selected.
The oscillator may include multiple OR gates connected in series and connected to the pulse generat
Christie Parker & Hale LLP
Lam Tuan T.
Vitesse Semiconductor Corp.
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