Method and apparatus for generating a status word in a pipelined

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395569, 3642319, 3642624, 3642632, 364DIG1, G06F 900

Patent

active

055903592

ABSTRACT:
A method and apparatus for generating status information about a pipelined processor after the completion of an execution of an instruction. A first storage device stores the current overall status of the processor due to the execution of a plurality of instructions previous to the presently executing instruction. A second storage device stores an instruction status which represents the status of the processor due to the presently executing instruction alone. Logic generates a new overall status which represents the staus of the processor due to the execution of the present instruction and the previous instructions wherein the new overall status is generated from the instruction status and the current overall status.

REFERENCES:
patent: 4295193 (1981-10-01), Pomerene
patent: 4903264 (1990-02-01), Talgam et al.
patent: 4956767 (1990-09-01), Stephenson
patent: 5134693 (1992-07-01), Saini

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