Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
1999-02-24
2001-08-21
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C327S180000, C327S551000
Reexamination Certificate
active
06278312
ABSTRACT:
BACKGROUND
1. Field of the Disclosure
The present disclosure pertains to the field of signal transmission. More particularly, the present disclosure pertains to deriving a reference voltage from two complementary signals and, in some embodiments, the use of such a reference voltage in facilitating the transmission and reception of signals between two circuits.
2. Description of Related Art
As integrated circuits and other electronic components are continually improved, data transfer rates between such components typically increase. One significant problem with transmitting signals between components at faster rates is that signal noise tends to obscure the underlying signal. Improved techniques to contend with signal noise may advantageously allow faster inter or intra-component signaling or more efficient signal drivers and/or receivers.
One noise component associated with switching of large or numerous driver circuits is caused by the large amount of current drawn when such drivers switch. Additionally, the normal operation of a component can introduce noise to the power supply of the component. Any such noise may affect the quality of signals transmitted to other components.
One prior art technique for transmitting signals is shown in
FIG. 1. A
driver block
100
includes a reference voltage generator
102
formed by a resistor
110
and a resistor
105
coupled together in a voltage divider arrangement between the supply voltage (Vcc) and ground of the driver block
100
. As a result, a reference voltage (Vref), which reflects noise in the Vcc and ground rails of the driver block
100
, is provided on a signal line
130
(see also, e.g., “A 900 Mb/s Bidirectional Signaling Scheme,” IEEE
Journal of Solid
-
State Circuits
, Vol. 30, No. 12, December 1995). The driver block
100
also includes a signal driver
115
which drives a data signal on a signal line
135
, and a clock driver
140
that drives a clock signal on a signal line
142
in conjunction with or synchronized with the data signal.
A receiver block
150
includes an input circuit
160
, such as a differential sense amplifier, which is coupled to receive both the data signal and the reference voltage. The input circuit
160
substantially subtracts or cancels common mode noise (noise from common sources coupled in both signals and the reference voltage), thereby obtaining a cleaner data signal at node
165
. Both noise from the driver and noise introduced by interconnect may be coupled in the reference voltage and the data signal. Therefore, such noise may be reduced or eliminated from the data signal using the common mode reference voltage. This type of arrangement is known as a psuedo-differential technique because it uses only signal(s) and a reference voltage rather than two complementary signals as used in a differential scheme. The output of the input circuit
160
is latched by a latch
170
clocked by the clock signal from the clock driver
140
.
Unfortunately, this technique requires a dedicated signal line and input and output interfaces (e.g., pins or connector balls in the case of integrated circuits), often raising the cost of the system. Additionally, older systems typically do not have a dedicated reference voltage line, and compatibility may restrict introduction of a new dedicated interface. Therefore, the need for additional pins is a disadvantage of this prior art approach.
SUMMARY
A disclosed apparatus includes a driver circuit and a receiver circuit. The driver circuit is coupled to drive two complementary signals and the receiver is coupled to receive the two complementary signals. The receiver circuit generates a reference voltage from the two complementary signals.
REFERENCES:
patent: 4588905 (1986-05-01), Kojima
patent: 4631737 (1986-12-01), Davis et al.
patent: 5574634 (1996-11-01), Parlour et al.
patent: 5760648 (1998-06-01), Koifman et al.
patent: 5856750 (1999-01-01), Koseki
patent: 5973515 (1999-10-01), Marbot et al.
patent: 6037824 (2000-03-01), Takahashi
Dabral Sanjay
Zeng Ming
Cunningham Terry D.
Intel Corporation
Lam Peter
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