Method and apparatus for generating a real address multiple virt

Details Method and apparatus for generating a real address multiple virt Method and apparatus for generating a real address multiple virt

1988-02-16

1991-01-15

Fleming, Michael R.

Boots, shoes, and leggings

364900, 3642563, 3649612, 3642466, G06F 1210

Patent

active

049858289

ABSTRACT:
A multiple virtual space control in a multiple virtual storage system having an address translation table used to translate a logical address to a real address, a control register for holding a start address of the address translation table or a space identifier (hereinafter represented by address translation table start address) and an address translation buffer containing a pair of logical address and real address and an address translation table start address for translating a logical address to a real address, in order to update the content of the control register to switch the virtual space. A group identifier comprising a plurality of bits for identifying an area common to a group of virtual spaces is added to an entry of the address translation table, an entry of the address translation buffer and the control register. When a logical address is to be translated to a real address, if there is an entry having a logical address and an address translation table start address equal to the memory request logical address and the address translation table start address of the control register, or an entry having a logical address and a group identifier equal to the memory request logical address and the group identifier of the control register, in the address translation buffer, the real address of the entry is rendered valid and used for memory access.

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patent: 4812969 (1989-03-01), Takagi et al.
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