Method and apparatus for generating a data sampling clock locked

Details Method and apparatus for generating a data sampling clock locked Method and apparatus for generating a data sampling clock locked

1988-04-01

1989-07-18

Miller, Stanley D.

Pulse or digital communications

Repeaters

Testing

375 8, 375120, 328155, 307262, 307511, H03K 117, H03K 700

Patent

active

048497037

ABSTRACT:
An improved baud clock recovery, synchronization and data sampling circuit for a modem. A CODEC (41) samples the incoming signal at a rate determined by the sample clock output of a presettable counter (236). The sampled signal is then squared (231) and bandpass filtered (232) to provide a recovered baud clock. A detector (233) signals the positive going zero-crossing points of the recovered baud clock. A lead/lag calculator (234) determines which of the signal samples is nearest the zero-crossing point. The calculator (234) then determines whether this and every subsequent 12th sampling point leads or lags the zero-crossing point by inspecting the sign of the recovered baud clock and adjusts the preset inputs of the counter (236) to cause the sample points to occur at the zero-crossing point.

REFERENCES:
patent: 4280099 (1981-07-01), Rattlingourd
patent: 4400817 (1983-08-01), Sumner
patent: 4455661 (1984-06-01), Qureshi
patent: 4472818 (1984-09-01), Zapisek et al.
patent: 4488294 (1984-12-01), Christensen et al.
patent: 4538119 (1985-08-01), Ashida
patent: 4570125 (1986-02-01), Gibson
patent: 4620294 (1986-10-01), Leung et al.
patent: 4680780 (1987-07-01), Agoston et al.

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