Data processing: measuring – calibrating – or testing – Testing system – Of circuit
Reexamination Certificate
2001-12-14
2004-03-09
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Testing system
Of circuit
C714S720000, C714S738000
Reexamination Certificate
active
06704677
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to testing buses for computer systems. More specifically, the present invention relates to a method and an apparatus that facilitates generating a data pattern for simultaneously testing multiple bus widths.
2. Related Art
Modern computing systems often include multiple buses having different bus widths to couple together the various components of the system. These buses can include internal buses within a computer system component and external buses that couple the various computer system components together. Testing multiple buses that have different bus widths presents a number of problems to a test engineer.
One objective of testing a bus is to generate a maximum number of signal transitions on the bus. Generating a maximum number of signal level transitions on a bus can cause the bus to generate the maximum amount of electrical noise. Additionally, generating the maximum number of signal level transitions allows a tester to determine that the bus is free of signal crosstalk which may cause signal level margin and signal timing margins to be out of specification.
One method of selecting a data pattern that can cause all of the signal lines on a bus to switch simultaneously is to switch between all zeros and all ones. For example, a 32-bit data bus can be driven with alternating patterns of 0x00000000 and 0xFFFFFFFF to induce maximum stress on the bus. This method is effective when only 32-bit data buses are involved in testing. However, this method is not effective when more than one data bus width is being tested simultaneously.
FIG. 1
illustrates the process of testing a 1-bit data bus coupled to a 64-bit data bus using parallel to serial converter
106
. As shown in
FIG. 1
, the system under test includes 64-bit CPU
102
and parallel to serial converter
106
coupled together by 64-bit bus
104
. The output of parallel to serial converter
106
is 1-bit bus
108
.
During the testing process, test pattern
114
is applied to the system to test the buses. In particular, test pattern
114
is selected to test 1-bit bus
108
and, in fact, provides the maximum transitions on 1-bit bus
108
as shown in 1-bit bus transitions
112
. This pattern, however, does not provide any transitions on the 64-bit bus. Each line of 64-bit bus
104
is held at either a high level or a low level, but none of the lines of 64-bit bus
104
have any transitions as shown in 64-bit bus transitions
110
.
FIG. 2
illustrates the process of testing a 4-bit data bus coupled to a 64-bit data bus using wide bus to narrow bus converter
206
. As shown in
FIG. 2
, the system under test includes 64-bit CPU
202
and wide bus to narrow bus converter
206
coupled together by 64-bit bus
204
. The output of wide bus to narrow bus converter
206
is 4-bit bus
208
.
During the testing process, test pattern
214
is applied to the system to test the buses. In particular, test pattern
214
is selected to test 4-bit bus
208
and, in fact, provides the maximum transitions on 4-bit bus
208
as shown in 4-bit bus transitions
212
. This pattern, however, does not provide any transitions on 64-bit bus
204
. Each line of 64-bit bus
204
is held at either a high level or a low level, but none of the lines of 64-bit bus
204
have any transitions as shown in 64-bit bus transitions
210
.
FIG. 3
illustrates the process of testing a 64-bit data bus coupled to a 4-bit data bus using wide bus to narrow bus converter
306
. As shown in
FIG. 3
, the system under test includes 64-bit CPU
302
and wide bus to narrow bus converter
306
coupled together by 64-bit bus
304
. The output of wide bus to narrow bus converter
306
is 4-bit bus
308
.
During the testing process, test pattern
314
is applied to the system to test the buses. In particular, test pattern
314
is selected to test 64-bit bus
304
and, in fact, provides the maximum transitions on 64-bit bus
304
as shown in 64-bit bus transitions
310
. This pattern, however, provides only one transition on 4-bit bus
308
for every sixteen bit-times as shown in 4-bit bus transitions
312
.
FIGS. 2 and 3
, taken together illustrate the problem encountered when testing buses with different widths. This testing provides maximum transitions to one bus while the other buses have no transitions or a minimal number of transitions. Thus, only one bus is adequately tested by each test pattern and the tester needs to develop several tests, one for each bus width, to adequately test the system.
What is needed is a method and an apparatus that facilitates generating a bus testing data pattern that does not exhibit the problems described above.
SUMMARY
One embodiment of the present invention provides a system that facilitates generating a bus testing data pattern for simultaneously testing multiple bus widths. The system first receives a list of bus widths to be tested. Next, the system receives a root test pattern with a width equal to the width of the smallest bus in the list. The system then extends this test pattern by inverting each bit of the root test pattern and concatenating this inverted pattern with the root test pattern. Next, the system creates an additional test pattern by repeating the second test pattern a sufficient number of times so that the width of this additional test pattern equals the width of the next larger bus. The system then creates a test pattern for the next larger bus by inverting each bit of the additional test pattern and concatenating this inverted test pattern with the additional test pattern. The test pattern can be used to simultaneously test the smallest bus width and the next larger bus width in the list of bus widths.
In one embodiment of the present invention, while larger bus widths remain in the list of bus widths the system repeats the steps of creating an additional test pattern by repeating the immediately previous test pattern sufficient times so that this additional test pattern width equals the width of the next larger bus in the list and then creating a second additional test pattern by inverting each bit of the first additional test pattern which is then concatenated with the first additional test pattern.
In one embodiment of the present invention, the system transmits a final test pattern created by this process through a set of buses related to the list of bus widths.
In one embodiment of the present invention, the system uses a final test pattern created by this process to test a set of buses related to the list of bus widths.
In one embodiment of the present invention, the final test pattern created by this process provides maximum transitional stress to each data bus.
In one embodiment of the present invention, if the list of bus widths is not available the system creates a default list of bus widths and uses the default list of bus widths as the list of bus widths to be tested.
In one embodiment of the present invention creating the default list of bus widths involves using one bit as a default smallest bus width and then assigning additional bus widths as increasing powers-of-two until a specified largest bus width is reached.
REFERENCES:
patent: 4459694 (1984-07-01), Ueno et al.
patent: 5457696 (1995-10-01), Mori
patent: 5475815 (1995-12-01), Byers et al.
patent: 6317851 (2001-11-01), Kobayashi
patent: 6609221 (2003-08-01), Coyle et al.
Grundler Edward J.
Hoff Marc S.
Kim Paul
Park, Vaughn & Fleming LLP
Sun Microsystems Inc.
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