Method and apparatus for generating a correction signal in a dig

Pulse or digital communications – Spread spectrum – Direct sequence

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307262, 328155, H03D 324

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active

049550403

ABSTRACT:
A digital clock recovery system according to the prior art contains a phase sensor with a delay device. This cannot be implemented with the required accuracy in integrated circuit technology. The invention does not required any delay device for its implementation. A phase sensor (6) does not compare the phase relationship of the active edges of the pulses of a digital signal (DS) with a first auxiliary data clock (DHT1) which acts as clock recovered from the digital signal (DS), but instead, at phase sensor (6) compares the phase relationship of the active edges of the pulses of the digital signal (DS) and a second auxiliary data clock (DHT2) which has a defined phase difference relative to the first auxiliary data clock (DHT1). If the comparison does not result in a phase difference, a correction signal (K) is generated which causes a phase correction of both of the auxiliary data clocks (DHT1, DHT2) which produce the defined phase difference. Digital clock recovery devices are used in digital signal multiplexing devices and distributor multiplexors between, in particular, higher levels of a digital signal hierarchy.

REFERENCES:
patent: 3582789 (1969-01-01), Mick
patent: 4320515 (1982-03-01), Burton, Jr.
patent: 4348762 (1982-09-01), Shiun et al.
patent: 4400667 (1983-08-01), Belkin
patent: 4573173 (1986-02-01), Yoshida
patent: 4672639 (1987-06-01), Tanabe et al.
patent: 4780889 (1988-10-01), Ley et al.
"IBM Technical Disclosure Bulletin", vol. 29, No. 2, Jul. 1986, pp. 903-904.

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