Method and apparatus for generating a clock signal in...

Oscillators – Automatic frequency stabilization using a phase or frequency... – Plural oscillators controlled

Reexamination Certificate

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Details

C331S017000, C331S00100A, C331S049000, C327S156000, C327S159000

Reexamination Certificate

active

07148753

ABSTRACT:
A first phase-locked loop circuit that includes a crystal oscillator, receives a reference clock signal and supplies a first phase-locked loop output signal based on the reference clock during normal operational mode and a stored value in holdover mode. A second phase-locked loop circuit receives the first phase-locked loop output signal and utilizes the first phase-locked loop output signal when generating an output clock in holdover mode. The second phase-locked loop utilizes the first phase-locked loop output signal during operation in the holdover mode to generate the output clock and utilizes the reference clock during normal operational mode to generate the output clock. Alternatively, the second phase-locked loop utilizes the first phase-locked loop output signal both during operation in the holdover mode and during normal operational mode to generate the output clock. The first phased-lock loop circuit may include a low pass filter coupled to the loop filter, which supplies a low pass filtered signal to the crystal oscillator in holdover mode. The first phased-lock loop circuit may include a low pass filter and a delay circuit coupled to the loop filter, which supply a delayed and low pass filtered signal to the crystal oscillator in holdover mode.

REFERENCES:
patent: 5053726 (1991-10-01), Christopher et al.
patent: 5534822 (1996-07-01), Taniguchi et al.
patent: 5572167 (1996-11-01), Alder et al.
patent: 5726607 (1998-03-01), Brede et al.
patent: 6804316 (2004-10-01), Shectman
Raltron, “Synchronous Equipment OCXO Based Stratum 3 Clock Unit—SY01-S3”, May 20, 2002.

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