Method and apparatus for generating a clock signal having a freq

Details Method and apparatus for generating a clock signal having a freq Method and apparatus for generating a clock signal having a freq

1997-05-19

1999-09-28

Wambach, Margaret R.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Using shift register

377 33, 377 48, 327299, G11C 1900

Patent

active

059600535

ABSTRACT:
A method and apparatus for dividing a clock circuit employs a device having a first counting element capable of repetitively incrementing through the first plurality of states and a second counting element, having a second number of states, that generates a second output bit and repetitively increments through the second plurality of states. The first counting element is responsive to the second output bit of the second counting element and the reset signal input of the second counting element is responsive to at least one of the first plurality of output bits so that the second counting element resets to an initial state either when the oscillator signal is asserted and the second counting element counts through each of the second plurality of states or when the oscillator signal is asserted and the reset signal input is asserted and the second counting element has incremented through a preselected number of the second plurality of states. The first counting element increments whenever both the oscillator signal and the enable signal input are asserted. The first counting element and the second counting element, combined, have a predetermined third number of states. A circuit, responsive to the first plurality of output bits from the first counting element and the second output bit from the second counting element, asserts a quasi-periodic pulsed signal during a preselected subset of the third number of states, so that the quasi-periodic pulsed signal has a mean frequency equal to oscillator frequency divided by a fraction.

REFERENCES:
patent: 5748949 (1998-05-01), Johnston

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