Method and apparatus for generating a 48-bit frame check sequenc

Details Method and apparatus for generating a 48-bit frame check sequenc Method and apparatus for generating a 48-bit frame check sequenc

1991-01-30

1994-04-26

Beausoliel, Jr., Robert W.

Excavating

371 53, G06F 1110, H03M 1300

Patent

active

053073550

ABSTRACT:
A node operating in a network using the International Standard Organization (ISO) High-Level Data Link Control (HDLC) network protocol includes a mechanism for encoding information such that frames including the encoded information can be correctly interpreted by nodes operating in either of the standard 16-bit or 32-bit ISO-HDLC operating modes. The encoding mechanism produces a preliminary frame check sequence by encoding the information in an encoder using a generator polynomial G.sub.48 (x), which is a combination of the generator polynomials G.sub.16 (x) and G.sub.32 (x) which are used to produce frame check sequences for nodes operating in 16-bit or 32-bit modes, respectively. Before the information is encoded, the encoding mechanism sets the encoder to an initial condition using an initializing polynomial I.sub.48 (x). The preliminary frame check sequence is further encoded by adding to it a complementing polynomial C.sub.48 (x). The result is a 48-bit frame check sequence. The encoding mechanism appends the 48-bit frame check sequence to the information, and transmits the information and the appended 48-bit frame check sequence over the network as part of a frame.

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